diff options
Diffstat (limited to 'passes/cmds/splice.cc')
| -rw-r--r-- | passes/cmds/splice.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index ea9e06979..0f63b91c5 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -211,7 +211,7 @@ struct SpliceWorker std::vector<Wire*> mod_wires = module->wires(); for (auto wire : mod_wires) - if ((!no_outputs && wire->port_output) || (do_wires && wire->name[0] == '\\')) { + if ((!no_outputs && wire->port_output) || (do_wires && wire->name.isPublic())) { if (!design->selected(module, wire)) continue; RTLIL::SigSpec sig = sigmap(wire); @@ -246,7 +246,7 @@ struct SpliceWorker struct SplicePass : public Pass { SplicePass() : Pass("splice", "create explicit splicing cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -287,7 +287,7 @@ struct SplicePass : public Pass { log("by selected wires are rewired.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool sel_by_cell = false; bool sel_by_wire = false; |