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-rw-r--r--passes/cmds/stat.cc227
1 files changed, 114 insertions, 113 deletions
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 19cdaa621..b21ba01ba 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -21,145 +21,145 @@
#include "kernel/celltypes.h"
#include "kernel/log.h"
-namespace
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct statdata_t
{
- struct statdata_t
+ #define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
+ X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
+
+ #define X(_name) int _name;
+ STAT_INT_MEMBERS
+ #undef X
+
+ std::map<RTLIL::IdString, int> num_cells_by_type;
+
+ statdata_t operator+(const statdata_t &other) const
{
- #define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
- X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
+ statdata_t sum = other;
+ #define X(_name) sum._name += _name;
+ STAT_INT_MEMBERS
+ #undef X
+ for (auto &it : num_cells_by_type)
+ sum.num_cells_by_type[it.first] += it.second;
+ return sum;
+ }
- #define X(_name) int _name;
+ statdata_t operator*(int other) const
+ {
+ statdata_t sum = *this;
+ #define X(_name) sum._name *= other;
STAT_INT_MEMBERS
- #undef X
+ #undef X
+ for (auto &it : sum.num_cells_by_type)
+ it.second *= other;
+ return sum;
+ }
- std::map<RTLIL::IdString, int> num_cells_by_type;
+ statdata_t()
+ {
+ #define X(_name) _name = 0;
+ STAT_INT_MEMBERS
+ #undef X
+ }
- statdata_t operator+(const statdata_t &other) const
- {
- statdata_t sum = other;
- #define X(_name) sum._name += _name;
- STAT_INT_MEMBERS
- #undef X
- for (auto &it : num_cells_by_type)
- sum.num_cells_by_type[it.first] += it.second;
- return sum;
- }
+ statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
+ {
+ #define X(_name) _name = 0;
+ STAT_INT_MEMBERS
+ #undef X
- statdata_t operator*(int other) const
+ for (auto &it : mod->wires_)
{
- statdata_t sum = *this;
- #define X(_name) sum._name *= other;
- STAT_INT_MEMBERS
- #undef X
- for (auto &it : sum.num_cells_by_type)
- it.second *= other;
- return sum;
+ if (!design->selected(mod, it.second))
+ continue;
+
+ if (it.first[0] == '\\') {
+ num_pub_wires++;
+ num_pub_wire_bits += it.second->width;
+ }
+
+ num_wires++;
+ num_wire_bits += it.second->width;
}
- statdata_t()
- {
- #define X(_name) _name = 0;
- STAT_INT_MEMBERS
- #undef X
+ for (auto &it : mod->memories) {
+ if (!design->selected(mod, it.second))
+ continue;
+ num_memories++;
+ num_memory_bits += it.second->width * it.second->size;
}
- statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
+ for (auto &it : mod->cells_)
{
- #define X(_name) _name = 0;
- STAT_INT_MEMBERS
- #undef X
-
- for (auto &it : mod->wires_)
- {
- if (!design->selected(mod, it.second))
- continue;
-
- if (it.first[0] == '\\') {
- num_pub_wires++;
- num_pub_wire_bits += it.second->width;
- }
-
- num_wires++;
- num_wire_bits += it.second->width;
- }
+ if (!design->selected(mod, it.second))
+ continue;
- for (auto &it : mod->memories) {
- if (!design->selected(mod, it.second))
- continue;
- num_memories++;
- num_memory_bits += it.second->width * it.second->size;
- }
+ RTLIL::IdString cell_type = it.second->type;
- for (auto &it : mod->cells_)
+ if (width_mode)
{
- if (!design->selected(mod, it.second))
- continue;
-
- RTLIL::IdString cell_type = it.second->type;
-
- if (width_mode)
- {
- if (cell_type.in("$not", "$pos", "$neg",
- "$logic_not", "$logic_and", "$logic_or",
- "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
- "$lut", "$and", "$or", "$xor", "$xnor",
- "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
- "$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
- int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
- int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
- int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
- cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
- }
- else if (cell_type.in("$mux", "$pmux"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
- else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
+ if (cell_type.in("$not", "$pos", "$neg",
+ "$logic_not", "$logic_and", "$logic_or",
+ "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
+ "$lut", "$and", "$or", "$xor", "$xnor",
+ "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
+ "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
+ "$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
+ int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
+ int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
+ int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
+ cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
}
-
- num_cells++;
- num_cells_by_type[cell_type]++;
+ else if (cell_type.in("$mux", "$pmux"))
+ cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
+ else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
+ cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
}
- for (auto &it : mod->processes) {
- if (!design->selected(mod, it.second))
- continue;
- num_processes++;
- }
+ num_cells++;
+ num_cells_by_type[cell_type]++;
}
- void log_data()
- {
- log(" Number of wires: %6d\n", num_wires);
- log(" Number of wire bits: %6d\n", num_wire_bits);
- log(" Number of public wires: %6d\n", num_pub_wires);
- log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
- log(" Number of memories: %6d\n", num_memories);
- log(" Number of memory bits: %6d\n", num_memory_bits);
- log(" Number of processes: %6d\n", num_processes);
- log(" Number of cells: %6d\n", num_cells);
- for (auto &it : num_cells_by_type)
- log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
+ for (auto &it : mod->processes) {
+ if (!design->selected(mod, it.second))
+ continue;
+ num_processes++;
}
- };
+ }
- statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
+ void log_data()
{
- statdata_t mod_data = mod_stat.at(mod);
- std::map<RTLIL::IdString, int> num_cells_by_type;
- num_cells_by_type.swap(mod_data.num_cells_by_type);
-
+ log(" Number of wires: %6d\n", num_wires);
+ log(" Number of wire bits: %6d\n", num_wire_bits);
+ log(" Number of public wires: %6d\n", num_pub_wires);
+ log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
+ log(" Number of memories: %6d\n", num_memories);
+ log(" Number of memory bits: %6d\n", num_memory_bits);
+ log(" Number of processes: %6d\n", num_processes);
+ log(" Number of cells: %6d\n", num_cells);
for (auto &it : num_cells_by_type)
- if (mod_stat.count(it.first) > 0) {
- log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
- mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
- mod_data.num_cells -= it.second;
- } else {
- mod_data.num_cells_by_type[it.first] += it.second;
- }
-
- return mod_data;
+ log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
}
+};
+
+statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
+{
+ statdata_t mod_data = mod_stat.at(mod);
+ std::map<RTLIL::IdString, int> num_cells_by_type;
+ num_cells_by_type.swap(mod_data.num_cells_by_type);
+
+ for (auto &it : num_cells_by_type)
+ if (mod_stat.count(it.first) > 0) {
+ log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
+ mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
+ mod_data.num_cells -= it.second;
+ } else {
+ mod_data.num_cells_by_type[it.first] += it.second;
+ }
+
+ return mod_data;
}
struct StatPass : public Pass {
@@ -243,3 +243,4 @@ struct StatPass : public Pass {
}
} StatPass;
+PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 07:42:54 +0000