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-rw-r--r--passes/cmds/bugpoint.cc28
-rw-r--r--passes/cmds/check.cc45
-rw-r--r--passes/cmds/connect.cc26
-rw-r--r--passes/cmds/connwrappers.cc22
-rw-r--r--passes/cmds/copy.cc4
-rw-r--r--passes/cmds/delete.cc43
-rw-r--r--passes/cmds/design.cc39
-rw-r--r--passes/cmds/rename.cc222
-rw-r--r--passes/cmds/scatter.cc28
-rw-r--r--passes/cmds/select.cc25
-rw-r--r--passes/cmds/setattr.cc36
-rw-r--r--passes/cmds/setundef.cc49
-rw-r--r--passes/cmds/show.cc94
-rw-r--r--passes/cmds/splice.cc32
-rw-r--r--passes/cmds/splitnets.cc3
-rw-r--r--passes/cmds/stat.cc46
16 files changed, 332 insertions, 410 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index ed427693d..ad6a07fa0 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -114,8 +114,8 @@ struct BugpointPass : public Pass {
return design;
RTLIL::Design *design_copy = new RTLIL::Design;
- for (auto &it : design->modules_)
- design_copy->add(it.second->clone());
+ for (auto module : design->modules())
+ design_copy->add(module->clone());
Pass::call(design_copy, "proc_clean -quiet");
Pass::call(design_copy, "clean -purge");
@@ -127,21 +127,21 @@ struct BugpointPass : public Pass {
RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates)
{
RTLIL::Design *design_copy = new RTLIL::Design;
- for (auto &it : design->modules_)
- design_copy->add(it.second->clone());
+ for (auto module : design->modules())
+ design_copy->add(module->clone());
int index = 0;
if (modules)
{
- for (auto &it : design_copy->modules_)
+ for (auto module : design_copy->modules())
{
- if (it.second->get_blackbox_attribute())
+ if (module->get_blackbox_attribute())
continue;
if (index++ == seed)
{
- log("Trying to remove module %s.\n", it.first.c_str());
- design_copy->remove(it.second);
+ log("Trying to remove module %s.\n", module->name.c_str());
+ design_copy->remove(module);
return design_copy;
}
}
@@ -178,12 +178,12 @@ struct BugpointPass : public Pass {
if (mod->get_blackbox_attribute())
continue;
- for (auto &it : mod->cells_)
+ for (auto cell : mod->cells())
{
if (index++ == seed)
{
- log("Trying to remove cell %s.%s.\n", mod->name.c_str(), it.first.c_str());
- mod->remove(it.second);
+ log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str());
+ mod->remove(cell);
return design_copy;
}
}
@@ -285,7 +285,7 @@ struct BugpointPass : public Pass {
}
}
}
- return NULL;
+ return nullptr;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -433,8 +433,8 @@ struct BugpointPass : public Pass {
{
Pass::call(design, "design -reset");
crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
- for (auto &it : crashing_design->modules_)
- design->add(it.second->clone());
+ for (auto module : crashing_design->modules())
+ design->add(module->clone());
delete crashing_design;
}
}
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 63703b848..ba29e6f4b 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -98,49 +98,6 @@ struct CheckPass : public Pass {
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
- pool<IdString> fftypes;
- fftypes.insert(ID($sr));
- fftypes.insert(ID($ff));
- fftypes.insert(ID($dff));
- fftypes.insert(ID($dffe));
- fftypes.insert(ID($dffsr));
- fftypes.insert(ID($adff));
- fftypes.insert(ID($dlatch));
- fftypes.insert(ID($dlatchsr));
- fftypes.insert(ID($_DFFE_NN_));
- fftypes.insert(ID($_DFFE_NP_));
- fftypes.insert(ID($_DFFE_PN_));
- fftypes.insert(ID($_DFFE_PP_));
- fftypes.insert(ID($_DFFSR_NNN_));
- fftypes.insert(ID($_DFFSR_NNP_));
- fftypes.insert(ID($_DFFSR_NPN_));
- fftypes.insert(ID($_DFFSR_NPP_));
- fftypes.insert(ID($_DFFSR_PNN_));
- fftypes.insert(ID($_DFFSR_PNP_));
- fftypes.insert(ID($_DFFSR_PPN_));
- fftypes.insert(ID($_DFFSR_PPP_));
- fftypes.insert(ID($_DFF_NN0_));
- fftypes.insert(ID($_DFF_NN1_));
- fftypes.insert(ID($_DFF_NP0_));
- fftypes.insert(ID($_DFF_NP1_));
- fftypes.insert(ID($_DFF_N_));
- fftypes.insert(ID($_DFF_PN0_));
- fftypes.insert(ID($_DFF_PN1_));
- fftypes.insert(ID($_DFF_PP0_));
- fftypes.insert(ID($_DFF_PP1_));
- fftypes.insert(ID($_DFF_P_));
- fftypes.insert(ID($_DLATCHSR_NNN_));
- fftypes.insert(ID($_DLATCHSR_NNP_));
- fftypes.insert(ID($_DLATCHSR_NPN_));
- fftypes.insert(ID($_DLATCHSR_NPP_));
- fftypes.insert(ID($_DLATCHSR_PNN_));
- fftypes.insert(ID($_DLATCHSR_PNP_));
- fftypes.insert(ID($_DLATCHSR_PPN_));
- fftypes.insert(ID($_DLATCHSR_PPP_));
- fftypes.insert(ID($_DLATCH_N_));
- fftypes.insert(ID($_DLATCH_P_));
- fftypes.insert(ID($_FF_));
-
for (auto module : design->selected_whole_modules_warn())
{
if (module->has_processes_warn())
@@ -242,7 +199,7 @@ struct CheckPass : public Pass {
{
for (auto cell : module->cells())
{
- if (fftypes.count(cell->type) == 0)
+ if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index f93bada27..0b0868dfb 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -32,9 +32,9 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
- for (auto &it : module->cells_)
- for (auto &port : it.second->connections_)
- if (ct.cell_output(it.second->type, port.first))
+ for (auto cell : module->cells())
+ for (auto &port : cell->connections_)
+ if (ct.cell_output(cell->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);
for (auto &conn : module->connections_)
@@ -77,15 +77,13 @@ struct ConnectPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- RTLIL::Module *module = NULL;
- for (auto &it : design->modules_) {
- if (!design->selected(it.second))
- continue;
- if (module != NULL)
- log_cmd_error("Multiple modules selected: %s, %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.first));
- module = it.second;
+ RTLIL::Module *module = nullptr;
+ for (auto mod : design->selected_modules()) {
+ if (module != nullptr)
+ log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
+ module = mod;
}
- if (module == NULL)
+ if (module == nullptr)
log_cmd_error("No modules selected.\n");
if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n");
@@ -130,7 +128,7 @@ struct ConnectPass : public Pass {
std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
for (size_t i = 0; i < lhs.size(); i++)
- if (rhs[i].wire != NULL)
+ if (rhs[i].wire != nullptr)
sigmap.add(lhs[i], rhs[i]);
}
@@ -172,14 +170,14 @@ struct ConnectPass : public Pass {
if (flag_nounset)
log_cmd_error("Can't use -port together with -nounset.\n");
- if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0)
+ if (module->cell(RTLIL::escape_id(port_cell)) == nullptr)
log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
- module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));
+ module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));
}
else
log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 5a15cbbaf..6ae7c9304 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -65,15 +65,13 @@ struct ConnwrappersWorker
decls[key] = decl;
}
- void work(RTLIL::Design *design, RTLIL::Module *module)
+ void work(RTLIL::Module *module)
{
std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
SigMap sigmap(module);
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = it.second;
-
if (!decl_celltypes.count(cell->type))
continue;
@@ -105,13 +103,8 @@ struct ConnwrappersWorker
}
}
- for (auto &it : module->cells_)
+ for (auto cell : module->selected_cells())
{
- RTLIL::Cell *cell = it.second;
-
- if (!design->selected(module, cell))
- continue;
-
for (auto &conn : cell->connections_)
{
std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
@@ -141,8 +134,8 @@ struct ConnwrappersWorker
}
if (old_sig.size())
- log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
- RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
+ log("Connected extended bits of %s.%s:%s: %s -> %s\n", log_id(module->name), log_id(cell->name),
+ log_id(conn.first), log_signal(old_sig), log_signal(conn.second));
}
}
}
@@ -200,9 +193,8 @@ struct ConnwrappersPass : public Pass {
log_header(design, "Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- worker.work(design, mod_it.second);
+ for (auto module : design->selected_modules())
+ worker.work(module);
}
} ConnwrappersPass;
diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc
index acd2dba52..99f1f69cf 100644
--- a/passes/cmds/copy.cc
+++ b/passes/cmds/copy.cc
@@ -44,10 +44,10 @@ struct CopyPass : public Pass {
std::string src_name = RTLIL::escape_id(args[1]);
std::string trg_name = RTLIL::escape_id(args[2]);
- if (design->modules_.count(src_name) == 0)
+ if (design->module(src_name) == nullptr)
log_cmd_error("Can't find source module %s.\n", src_name.c_str());
- if (design->modules_.count(trg_name) != 0)
+ if (design->module(trg_name) != nullptr)
log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
RTLIL::Module *new_mod = design->module(src_name)->clone();
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 125bc96ca..b124e3b0f 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -65,27 +65,24 @@ struct DeletePass : public Pass {
}
extra_args(args, argidx, design);
- std::vector<RTLIL::IdString> delete_mods;
-
- for (auto &mod_it : design->modules_)
+ std::vector<RTLIL::Module *> delete_mods;
+ for (auto module : design->modules())
{
- if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
- delete_mods.push_back(mod_it.first);
+ if (design->selected_whole_module(module->name) && !flag_input && !flag_output) {
+ delete_mods.push_back(module);
continue;
}
- if (!design->selected_module(mod_it.first))
+ if (!design->selected_module(module->name))
continue;
- RTLIL::Module *module = mod_it.second;
-
if (flag_input || flag_output) {
- for (auto &it : module->wires_)
- if (design->selected(module, it.second)) {
+ for (auto wire : module->wires())
+ if (design->selected(module, wire)) {
if (flag_input)
- it.second->port_input = false;
+ wire->port_input = false;
if (flag_output)
- it.second->port_output = false;
+ wire->port_output = false;
}
module->fixup_ports();
continue;
@@ -96,20 +93,19 @@ struct DeletePass : public Pass {
pool<RTLIL::IdString> delete_procs;
pool<RTLIL::IdString> delete_mems;
- for (auto &it : module->wires_)
- if (design->selected(module, it.second))
- delete_wires.insert(it.second);
+ for (auto wire : module->selected_wires())
+ delete_wires.insert(wire);
for (auto &it : module->memories)
if (design->selected(module, it.second))
delete_mems.insert(it.first);
- for (auto &it : module->cells_) {
- if (design->selected(module, it.second))
- delete_cells.insert(it.second);
- if (it.second->type.in(ID($memrd), ID($memwr)) &&
- delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0)
- delete_cells.insert(it.second);
+ for (auto cell : module->cells()) {
+ if (design->selected(module, cell))
+ delete_cells.insert(cell);
+ if (cell->type.in(ID($memrd), ID($memwr)) &&
+ delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0)
+ delete_cells.insert(cell);
}
for (auto &it : module->processes)
@@ -134,9 +130,8 @@ struct DeletePass : public Pass {
module->fixup_ports();
}
- for (auto &it : delete_mods) {
- delete design->modules_.at(it);
- design->modules_.erase(it);
+ for (auto mod : delete_mods) {
+ design->remove(mod);
}
}
} DeletePass;
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 4fd43329f..cfe97067d 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -60,6 +60,11 @@ struct DesignPass : public Pass {
log("Push the current design to the stack and then clear the current design.\n");
log("\n");
log("\n");
+ log(" design -push-copy\n");
+ log("\n");
+ log("Push the current design to the stack without clearing the current design.\n");
+ log("\n");
+ log("\n");
log(" design -pop\n");
log("\n");
log("Reset the current design and pop the last design from the stack.\n");
@@ -94,6 +99,11 @@ struct DesignPass : public Pass {
log("The Verilog front-end remembers defined macros and top-level declarations\n");
log("between calls to 'read_verilog'. This command resets this memory.\n");
log("\n");
+ log(" design -delete <name>\n");
+ log("\n");
+ log("Delete the design previously saved under the given name.\n");
+ log("\n");
+
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -101,10 +111,11 @@ struct DesignPass : public Pass {
bool reset_mode = false;
bool reset_vlog_mode = false;
bool push_mode = false;
+ bool push_copy_mode = false;
bool pop_mode = false;
bool import_mode = false;
RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL;
- std::string save_name, load_name, as_name;
+ std::string save_name, load_name, as_name, delete_name;
std::vector<RTLIL::Module*> copy_src_modules;
size_t argidx;
@@ -126,6 +137,11 @@ struct DesignPass : public Pass {
push_mode = true;
continue;
}
+ if (!got_mode && args[argidx] == "-push-copy") {
+ got_mode = true;
+ push_copy_mode = true;
+ continue;
+ }
if (!got_mode && args[argidx] == "-pop") {
got_mode = true;
pop_mode = true;
@@ -179,6 +195,13 @@ struct DesignPass : public Pass {
as_name = args[++argidx];
continue;
}
+ if (!got_mode && args[argidx] == "-delete" && argidx+1 < args.size()) {
+ got_mode = true;
+ delete_name = args[++argidx];
+ if (saved_designs.count(delete_name) == 0)
+ log_cmd_error("No saved design '%s' found!\n", delete_name.c_str());
+ continue;
+ }
break;
}
@@ -307,7 +330,7 @@ struct DesignPass : public Pass {
}
}
- if (!save_name.empty() || push_mode)
+ if (!save_name.empty() || push_mode || push_copy_mode)
{
RTLIL::Design *design_copy = new RTLIL::Design;
@@ -321,7 +344,7 @@ struct DesignPass : public Pass {
if (saved_designs.count(save_name))
delete saved_designs.at(save_name);
- if (push_mode)
+ if (push_mode || push_copy_mode)
pushed_designs.push_back(design_copy);
else
saved_designs[save_name] = design_copy;
@@ -329,7 +352,7 @@ struct DesignPass : public Pass {
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
{
- for (auto mod : design->modules())
+ for (auto mod : design->modules().to_vector())
design->remove(mod);
design->selection_stack.clear();
@@ -368,6 +391,14 @@ struct DesignPass : public Pass {
pushed_designs.pop_back();
}
}
+
+ if (!delete_name.empty())
+ {
+ auto it = saved_designs.find(delete_name);
+ log_assert(it != saved_designs.end());
+ delete it->second;
+ saved_designs.erase(it);
+ }
}
} DesignPass;
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 9b1830b7b..7d6d84d42 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -32,27 +32,27 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
if (module->count_id(to_name))
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
- for (auto &it : module->wires_)
- if (it.first == from_name) {
- Wire *w = it.second;
- log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
- module->rename(w, to_name);
- if (w->port_id || flag_output) {
- if (flag_output)
- w->port_output = true;
- module->fixup_ports();
- }
- return;
- }
+ RTLIL::Wire *wire_to_rename = module->wire(from_name);
+ RTLIL::Cell *cell_to_rename = module->cell(from_name);
- for (auto &it : module->cells_)
- if (it.first == from_name) {
+ if (wire_to_rename != nullptr) {
+ log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), log_id(to_name), log_id(module));
+ module->rename(wire_to_rename, to_name);
+ if (wire_to_rename->port_id || flag_output) {
if (flag_output)
- log_cmd_error("Called with -output but the specified object is a cell.\n");
- log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
- module->rename(it.second, to_name);
- return;
+ wire_to_rename->port_output = true;
+ module->fixup_ports();
}
+ return;
+ }
+
+ if (cell_to_rename != nullptr) {
+ if (flag_output)
+ log_cmd_error("Called with -output but the specified object is a cell.\n");
+ log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), log_id(to_name), log_id(module));
+ module->rename(cell_to_rename, to_name);
+ return;
+ }
log_cmd_error("Object `%s' not found!\n", from_name.c_str());
}
@@ -66,26 +66,26 @@ static std::string derive_name_from_src(const std::string &src, int counter)
return stringf("\\%s$%d", src_base.c_str(), counter);
}
-static IdString derive_name_from_wire(const RTLIL::Cell &cell)
+static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
{
// Find output
const SigSpec *output = nullptr;
int num_outputs = 0;
- for (auto &connection : cell.connections()) {
- if (cell.output(connection.first)) {
+ for (auto &connection : cell->connections()) {
+ if (cell->output(connection.first)) {
output = &connection.second;
num_outputs++;
}
}
if (num_outputs != 1) // Skip cells thad drive multiple outputs
- return cell.name;
+ return cell->name;
std::string name = "";
for (auto &chunk : output->chunks()) {
// Skip cells that drive privately named wires
if (!chunk.wire || chunk.wire->name.str()[0] == '$')
- return cell.name;
+ return cell->name;
if (name != "")
name += "$";
@@ -99,7 +99,7 @@ static IdString derive_name_from_wire(const RTLIL::Cell &cell)
}
}
- return name + cell.type.str();
+ return name + cell->type.str();
}
struct RenamePass : public Pass {
@@ -210,30 +210,25 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->selected_modules())
{
int counter = 0;
+ dict<RTLIL::Wire *, IdString> new_wire_names;
+ dict<RTLIL::Cell *, IdString> new_cell_names;
+
+ for (auto wire : module->selected_wires())
+ if (wire->name[0] == '$')
+ new_wire_names.emplace(wire, derive_name_from_src(wire->get_src_attribute(), counter++));
+
+ for (auto cell : module->selected_cells())
+ if (cell->name[0] == '$')
+ new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++));
- RTLIL::Module *module = mod.second;
- if (!design->selected(module))
- continue;
-
- dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
- for (auto &it : module->wires_) {
- if (it.first[0] == '$' && design->selected(module, it.second))
- it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
- new_wires[it.second->name] = it.second;
- }
- module->wires_.swap(new_wires);
- module->fixup_ports();
-
- dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells_) {
- if (it.first[0] == '$' && design->selected(module, it.second))
- it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
- new_cells[it.second->name] = it.second;
- }
- module->cells_.swap(new_cells);
+ for (auto &it : new_wire_names)
+ module->rename(it.first, it.second);
+
+ for (auto &it : new_cell_names)
+ module->rename(it.first, it.second);
}
}
else
@@ -241,19 +236,13 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
- {
- RTLIL::Module *module = mod.second;
- if (!design->selected(module))
- continue;
-
- dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells_) {
- if (it.first[0] == '$' && design->selected(module, it.second))
- it.second->name = derive_name_from_wire(*it.second);
- new_cells[it.second->name] = it.second;
- }
- module->cells_.swap(new_cells);
+ for (auto module : design->selected_modules()) {
+ dict<RTLIL::Cell *, IdString> new_cell_names;
+ for (auto cell : module->selected_cells())
+ if (cell->name[0] == '$')
+ new_cell_names[cell] = derive_name_from_cell_output_wire(cell);
+ for (auto &it : new_cell_names)
+ module->rename(it.first, it.second);
}
}
else
@@ -261,32 +250,33 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->selected_modules())
{
int counter = 0;
+ dict<RTLIL::Wire *, IdString> new_wire_names;
+ dict<RTLIL::Cell *, IdString> new_cell_names;
+
+ for (auto wire : module->selected_wires())
+ if (wire->name[0] == '$') {
+ RTLIL::IdString buf;
+ do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
+ while (module->wire(buf) != nullptr);
+ new_wire_names[wire] = buf;
+ }
+
+ for (auto cell : module->selected_cells())
+ if (cell->name[0] == '$') {
+ RTLIL::IdString buf;
+ do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
+ while (module->cell(buf) != nullptr);
+ new_cell_names[cell] = buf;
+ }
- RTLIL::Module *module = mod.second;
- if (!design->selected(module))
- continue;
-
- dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
- for (auto &it : module->wires_) {
- if (it.first[0] == '$' && design->selected(module, it.second))
- do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
- while (module->count_id(it.second->name) > 0);
- new_wires[it.second->name] = it.second;
- }
- module->wires_.swap(new_wires);
- module->fixup_ports();
-
- dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells_) {
- if (it.first[0] == '$' && design->selected(module, it.second))
- do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
- while (module->count_id(it.second->name) > 0);
- new_cells[it.second->name] = it.second;
- }
- module->cells_.swap(new_cells);
+ for (auto &it : new_wire_names)
+ module->rename(it.first, it.second);
+
+ for (auto &it : new_cell_names)
+ module->rename(it.first, it.second);
}
}
else
@@ -294,30 +284,24 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod.second;
- if (!design->selected(module))
- continue;
-
- dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
- for (auto &it : module->wires_) {
- if (design->selected(module, it.second))
- if (it.first[0] == '\\' && it.second->port_id == 0)
- it.second->name = NEW_ID;
- new_wires[it.second->name] = it.second;
- }
- module->wires_.swap(new_wires);
- module->fixup_ports();
-
- dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
- for (auto &it : module->cells_) {
- if (design->selected(module, it.second))
- if (it.first[0] == '\\')
- it.second->name = NEW_ID;
- new_cells[it.second->name] = it.second;
- }
- module->cells_.swap(new_cells);
+ dict<RTLIL::Wire *, IdString> new_wire_names;
+ dict<RTLIL::Cell *, IdString> new_cell_names;
+
+ for (auto wire : module->selected_wires())
+ if (wire->name[0] == '\\' && wire->port_id == 0)
+ new_wire_names[wire] = NEW_ID;
+
+ for (auto cell : module->selected_cells())
+ if (cell->name[0] == '\\')
+ new_cell_names[cell] = NEW_ID;
+
+ for (auto &it : new_wire_names)
+ module->rename(it.first, it.second);
+
+ for (auto &it : new_cell_names)
+ module->rename(it.first, it.second);
}
}
else
@@ -329,7 +313,7 @@ struct RenamePass : public Pass {
IdString new_name = RTLIL::escape_id(args[argidx]);
RTLIL::Module *module = design->top_module();
- if (module == NULL)
+ if (module == nullptr)
log_cmd_error("No top module found!\n");
log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
@@ -345,27 +329,27 @@ struct RenamePass : public Pass {
if (!design->selected_active_module.empty())
{
- if (design->modules_.count(design->selected_active_module) > 0)
- rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name, flag_output);
+ if (design->module(design->selected_active_module) != nullptr)
+ rename_in_module(design->module(design->selected_active_module), from_name, to_name, flag_output);
}
else
{
if (flag_output)
log_cmd_error("Mode -output requires that there is an active module selected.\n");
- for (auto &mod : design->modules_) {
- if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
- to_name = RTLIL::escape_id(to_name);
- log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
- RTLIL::Module *module = mod.second;
- design->modules_.erase(module->name);
- module->name = to_name;
- design->modules_[module->name] = module;
- goto rename_ok;
+
+ RTLIL::Module *module_to_rename = nullptr;
+ for (auto module : design->modules())
+ if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
+ module_to_rename = module;
+ break;
}
- }
- log_cmd_error("Object `%s' not found!\n", from_name.c_str());
- rename_ok:;
+ if (module_to_rename != nullptr) {
+ to_name = RTLIL::escape_id(to_name);
+ log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
+ design->rename(module_to_rename, to_name);
+ } else
+ log_cmd_error("Object `%s' not found!\n", from_name.c_str());
}
}
}
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 7123ba9fb..a5ef95f02 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -46,25 +46,19 @@ struct ScatterPass : public Pass {
CellTypes ct(design);
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- for (auto &c : mod_it.second->cells_)
- for (auto &p : c.second->connections_)
- {
- RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
-
- if (ct.cell_output(c.second->type, p.first)) {
- RTLIL::SigSig sigsig(p.second, wire);
- mod_it.second->connect(sigsig);
- } else {
- RTLIL::SigSig sigsig(wire, p.second);
- mod_it.second->connect(sigsig);
+ for (auto cell : module->cells()) {
+ dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
+ for (auto conn : cell->connections())
+ new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
+ for (auto &it : new_connections) {
+ if (ct.cell_output(cell->type, it.first))
+ module->connect(RTLIL::SigSig(it.second.first, it.second.second));
+ else
+ module->connect(RTLIL::SigSig(it.second.second, it.second.first));
+ cell->setPort(it.first, it.second.second);
}
-
- p.second = wire;
}
}
}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b64b077e4..c04ff438a 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1007,6 +1007,7 @@ struct SelectPass : public Pass {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
+ log(" select [ -unset <name> ]\n");
log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
@@ -1029,6 +1030,10 @@ struct SelectPass : public Pass {
log(" under the given name (see @<name> below). to save the current selection,\n");
log(" use \"select -set <name> %%\"\n");
log("\n");
+ log(" -unset <name>\n");
+ log(" do not modify the current selection. instead remove a previously saved\n");
+ log(" selection under the given name (see @<name> below).");
+ log("\n");
log(" -assert-none\n");
log(" do not modify the current selection. instead assert that the given\n");
log(" selection is empty. i.e. produce an error if any object matching the\n");
@@ -1238,7 +1243,7 @@ struct SelectPass : public Pass {
int assert_max = -1;
int assert_min = -1;
std::string write_file, read_file;
- std::string set_name, sel_str;
+ std::string set_name, unset_name, sel_str;
work_stack.clear();
@@ -1310,6 +1315,10 @@ struct SelectPass : public Pass {
set_name = RTLIL::escape_id(args[++argidx]);
continue;
}
+ if (arg == "-unset" && argidx+1 < args.size()) {
+ unset_name = RTLIL::escape_id(args[++argidx]);
+ continue;
+ }
if (arg.size() > 0 && arg[0] == '-')
log_cmd_error("Unknown option %s.\n", arg.c_str());
bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1);
@@ -1358,8 +1367,11 @@ struct SelectPass : public Pass {
if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
- if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
- log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+ if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !unset_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
+ log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -unset, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+
+ if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !set_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
+ log_cmd_error("Option -unset can not be combined with -list, -write, -count, -add, -del, -set, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
@@ -1527,6 +1539,13 @@ struct SelectPass : public Pass {
return;
}
+ if (!unset_name.empty())
+ {
+ if (!design->selection_vars.erase(unset_name))
+ log_error("Selection '%s' does not exist!\n", unset_name.c_str());
+ return;
+ }
+
if (work_stack.size() == 0) {
RTLIL::Selection &sel = design->selection_stack.back();
if (sel.full_selection)
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 08abb94cb..515f5a4ef 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -38,7 +38,7 @@ struct setunset_t
value = RTLIL::Const(set_value.substr(1, GetSize(set_value)-2));
} else {
RTLIL::SigSpec sig_value;
- if (!RTLIL::SigSpec::parse(sig_value, NULL, set_value))
+ if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value))
log_cmd_error("Can't decode value '%s'!\n", set_value.c_str());
value = sig_value.as_const();
}
@@ -96,10 +96,8 @@ struct SetattrPass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = mod.second;
-
if (flag_mod) {
if (design->selected_whole_module(module->name))
do_setunset(module->attributes, setunset_list);
@@ -109,17 +107,17 @@ struct SetattrPass : public Pass {
if (!design->selected(module))
continue;
- for (auto &it : module->wires_)
- if (design->selected(module, it.second))
- do_setunset(it.second->attributes, setunset_list);
+ for (auto wire : module->wires())
+ if (design->selected(module, wire))
+ do_setunset(wire->attributes, setunset_list);
for (auto &it : module->memories)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
- for (auto &it : module->cells_)
- if (design->selected(module, it.second))
- do_setunset(it.second->attributes, setunset_list);
+ for (auto cell : module->cells())
+ if (design->selected(module, cell))
+ do_setunset(cell->attributes, setunset_list);
for (auto &it : module->processes)
if (design->selected(module, it.second))
@@ -208,19 +206,13 @@ struct SetparamPass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod.second;
-
- if (!design->selected(module))
- continue;
-
- for (auto &it : module->cells_)
- if (design->selected(module, it.second)) {
- if (!new_cell_type.empty())
- it.second->type = new_cell_type;
- do_setunset(it.second->parameters, setunset_list);
- }
+ for (auto cell : module->selected_cells()) {
+ if (!new_cell_type.empty())
+ cell->type = new_cell_type;
+ do_setunset(cell->parameters, setunset_list);
+ }
}
}
} SetparamPass;
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 5afd40923..8d973869e 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -149,7 +149,7 @@ struct SetundefPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- bool got_value = false;
+ int got_value = 0;
bool undriven_mode = false;
bool expose_mode = false;
bool init_mode = false;
@@ -170,31 +170,31 @@ struct SetundefPass : public Pass {
continue;
}
if (args[argidx] == "-zero") {
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_ZERO;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-one") {
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_ONE;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-anyseq") {
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_ANYSEQ;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-anyconst") {
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_ANYCONST;
worker.next_bit_state = 0;
continue;
}
if (args[argidx] == "-undef") {
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_UNDEF;
worker.next_bit_state = 0;
continue;
@@ -207,8 +207,8 @@ struct SetundefPass : public Pass {
params_mode = true;
continue;
}
- if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
- got_value = true;
+ if (args[argidx] == "-random" && argidx+1 < args.size()) {
+ got_value++;
worker.next_bit_mode = MODE_RANDOM;
worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
for (int i = 0; i < 10; i++)
@@ -221,7 +221,7 @@ struct SetundefPass : public Pass {
if (!got_value && expose_mode) {
log("Using default as -undef with -expose.\n");
- got_value = true;
+ got_value++;
worker.next_bit_mode = MODE_UNDEF;
worker.next_bit_state = 0;
}
@@ -229,7 +229,9 @@ struct SetundefPass : public Pass {
if (expose_mode && !undriven_mode)
log_cmd_error("Option -expose must be used with option -undriven.\n");
if (!got_value)
- log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n");
+ log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, -random <seed>, or -expose must be specified.\n");
+ else if (got_value > 1)
+ log_cmd_error("Only one of the options -zero, -one, -anyseq, -anyconst, or -random <seed> can be specified.\n");
if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST))
log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n");
@@ -359,34 +361,9 @@ struct SetundefPass : public Pass {
pool<SigBit> ffbits;
pool<Wire*> initwires;
- pool<IdString> fftypes;
- fftypes.insert(ID($dff));
- fftypes.insert(ID($dffe));
- fftypes.insert(ID($dffsr));
- fftypes.insert(ID($adff));
-
- std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
-
- for (auto c1 : list_np)
- fftypes.insert(stringf("$_DFF_%c_", c1));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- fftypes.insert(stringf("$_DFFE_%c%c_", c1, c2));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- for (auto c3 : list_01)
- fftypes.insert(stringf("$_DFF_%c%c%c_", c1, c2, c3));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- for (auto c3 : list_np)
- fftypes.insert(stringf("$_DFFSR_%c%c%c_", c1, c2, c3));
-
for (auto cell : module->cells())
{
- if (!fftypes.count(cell->type))
+ if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index c0e07b6e1..155ed0fcd 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -41,8 +41,6 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-using RTLIL::id2cstr;
-
#undef CLUSTER_CELLS_AND_PORTBOXES
struct ShowWorker
@@ -101,7 +99,7 @@ struct ShowWorker
{
sig.sort_and_unify();
for (auto &c : sig.chunks()) {
- if (c.wire != NULL)
+ if (c.wire != nullptr)
for (auto &s : color_selections)
if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0)
return stringf("color=\"%s\"", s.first.c_str());
@@ -218,7 +216,7 @@ struct ShowWorker
if (sig.is_chunk()) {
const RTLIL::SigChunk &c = sig.as_chunk();
- if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
+ if (c.wire != nullptr && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));
} else {
@@ -230,7 +228,7 @@ struct ShowWorker
return std::string();
}
- std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = NULL)
+ std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr)
{
std::string code;
std::string net = gen_signode_simple(sig);
@@ -287,7 +285,7 @@ struct ShowWorker
else
code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str());
}
- if (node != NULL)
+ if (node != nullptr)
*node = stringf("x%d", idx);
}
else
@@ -300,7 +298,7 @@ struct ShowWorker
net_conn_map[net].bits = sig.size();
net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
}
- if (node != NULL)
+ if (node != nullptr)
*node = net;
}
return code;
@@ -366,22 +364,20 @@ struct ShowWorker
std::set<std::string> all_sources, all_sinks;
std::map<std::string, std::string> wires_on_demand;
- for (auto &it : module->wires_) {
- if (!design->selected_member(module->name, it.first))
- continue;
+ for (auto wire : module->selected_wires()) {
const char *shape = "diamond";
- if (it.second->port_input || it.second->port_output)
+ if (wire->port_input || wire->port_output)
shape = "octagon";
- if (it.first[0] == '\\') {
+ if (wire->name[0] == '\\') {
fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n",
- id2num(it.first), shape, findLabel(it.first.str()),
- nextColor(RTLIL::SigSpec(it.second), "color=\"black\"").c_str());
- if (it.second->port_input)
- all_sources.insert(stringf("n%d", id2num(it.first)));
- else if (it.second->port_output)
- all_sinks.insert(stringf("n%d", id2num(it.first)));
+ id2num(wire->name), shape, findLabel(wire->name.str()),
+ nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str());
+ if (wire->port_input)
+ all_sources.insert(stringf("n%d", id2num(wire->name)));
+ else if (wire->port_output)
+ all_sinks.insert(stringf("n%d", id2num(wire->name)));
} else {
- wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
+ wires_on_demand[stringf("n%d", id2num(wire->name))] = wire->name.str();
}
}
@@ -398,15 +394,12 @@ struct ShowWorker
fprintf(f, "}\n");
}
- for (auto &it : module->cells_)
+ for (auto cell : module->selected_cells())
{
- if (!design->selected_member(module->name, it.first))
- continue;
-
std::vector<RTLIL::IdString> in_ports, out_ports;
- for (auto &conn : it.second->connections()) {
- if (!ct.cell_output(it.second->type, conn.first))
+ for (auto &conn : cell->connections()) {
+ if (!ct.cell_output(cell->type, conn.first))
in_ports.push_back(conn.first);
else
out_ports.push_back(conn.first);
@@ -419,12 +412,12 @@ struct ShowWorker
for (auto &p : in_ports)
label_string += stringf("<p%d> %s%s|", id2num(p), escape(p.str()),
- genSignedLabels && it.second->hasParam(p.str() + "_SIGNED") &&
- it.second->getParam(p.str() + "_SIGNED").as_bool() ? "*" : "");
+ genSignedLabels && cell->hasParam(p.str() + "_SIGNED") &&
+ cell->getParam(p.str() + "_SIGNED").as_bool() ? "*" : "");
if (label_string[label_string.size()-1] == '|')
label_string = label_string.substr(0, label_string.size()-1);
- label_string += stringf("}|%s\\n%s|{", findLabel(it.first.str()), escape(it.second->type.str()));
+ label_string += stringf("}|%s\\n%s|{", findLabel(cell->name.str()), escape(cell->type.str()));
for (auto &p : out_ports)
label_string += stringf("<p%d> %s|", id2num(p), escape(p.str()));
@@ -434,19 +427,19 @@ struct ShowWorker
label_string += "}}";
std::string code;
- for (auto &conn : it.second->connections()) {
- code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
- conn.second, ct.cell_output(it.second->type, conn.first));
+ for (auto &conn : cell->connections()) {
+ code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
+ conn.second, ct.cell_output(cell->type, conn.first));
}
#ifdef CLUSTER_CELLS_AND_PORTBOXES
if (!code.empty())
fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n",
- id2num(it.first), id2num(it.first), label_string.c_str(), findColor(it.first), code.c_str());
+ id2num(cell->name), id2num(cell->name), label_string.c_str(), findColor(cell->name), code.c_str());
else
#endif
fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s",
- id2num(it.first), label_string.c_str(), findColor(it.first.str()), code.c_str());
+ id2num(cell->name), label_string.c_str(), findColor(cell->name.str()), code.c_str());
}
for (auto &it : module->processes)
@@ -491,12 +484,12 @@ struct ShowWorker
{
bool found_lhs_wire = false;
for (auto &c : conn.first.chunks()) {
- if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
+ if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
found_lhs_wire = true;
}
bool found_rhs_wire = false;
for (auto &c : conn.second.chunks()) {
- if (c.wire == NULL || design->selected_member(module->name, c.wire->name))
+ if (c.wire == nullptr || design->selected_member(module->name, c.wire->name))
found_rhs_wire = true;
}
if (!found_lhs_wire || !found_rhs_wire)
@@ -572,23 +565,21 @@ struct ShowWorker
design->optimize();
page_counter = 0;
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- module = mod_it.second;
- if (!design->selected_module(module->name))
- continue;
+ module = mod;
if (design->selected_whole_module(module->name)) {
if (module->get_blackbox_attribute()) {
- // log("Skipping blackbox module %s.\n", id2cstr(module->name));
+ // log("Skipping blackbox module %s.\n", log_id(module->name));
continue;
} else
- if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) {
- log("Skipping empty module %s.\n", id2cstr(module->name));
+ if (module->cells().size() == 0 && module->connections().empty() && module->processes.empty()) {
+ log("Skipping empty module %s.\n", log_id(module->name));
continue;
} else
- log("Dumping module %s to page %d.\n", id2cstr(module->name), ++page_counter);
+ log("Dumping module %s to page %d.\n", log_id(module->name), ++page_counter);
} else
- log("Dumping selected parts of module %s to page %d.\n", id2cstr(module->name), ++page_counter);
+ log("Dumping selected parts of module %s to page %d.\n", log_id(module->name), ++page_counter);
handle_module();
}
}
@@ -802,13 +793,12 @@ struct ShowPass : public Pass {
if (format != "ps" && format != "dot") {
int modcount = 0;
- for (auto &mod_it : design->modules_) {
- if (mod_it.second->get_blackbox_attribute())
+ for (auto module : design->selected_modules()) {
+ if (module->get_blackbox_attribute())
continue;
- if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
+ if (module->cells().size() == 0 && module->connections().empty())
continue;
- if (design->selected_module(mod_it.first))
- modcount++;
+ modcount++;
}
if (modcount > 1)
log_cmd_error("For formats different than 'ps' or 'dot' only one module must be selected.\n");
@@ -835,7 +825,7 @@ struct ShowPass : public Pass {
FILE *f = fopen(dot_file.c_str(), "w");
if (custom_prefix)
yosys_output_files.insert(dot_file);
- if (f == NULL) {
+ if (f == nullptr) {
for (auto lib : libs)
delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
@@ -889,8 +879,8 @@ struct ShowPass : public Pass {
if (flag_pause) {
#ifdef YOSYS_ENABLE_READLINE
- char *input = NULL;
- while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != NULL) {
+ char *input = nullptr;
+ while ((input = readline("Press ENTER to continue (or type 'shell' to open a shell)> ")) != nullptr) {
if (input[strspn(input, " \t\r\n")] == 0)
break;
char *p = input + strspn(input, " \t\r\n");
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index f99090279..ea9e06979 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -102,7 +102,7 @@ struct SpliceWorker
for (auto &bit : sig.to_sigbit_vector())
{
- if (bit.wire == NULL)
+ if (bit.wire == nullptr)
{
if (last_bit == 0)
chunks.back().append(bit);
@@ -149,23 +149,23 @@ struct SpliceWorker
void run()
{
- log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name));
+ log("Splicing signals in module %s:\n", log_id(module->name));
driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm);
- for (auto &it : module->wires_)
- if (it.second->port_input) {
- RTLIL::SigSpec sig = sigmap(it.second);
+ for (auto wire : module->wires())
+ if (wire->port_input) {
+ RTLIL::SigSpec sig = sigmap(wire);
driven_chunks.insert(sig);
for (auto &bit : sig.to_sigbit_vector())
driven_bits.push_back(bit);
driven_bits.push_back(RTLIL::State::Sm);
}
- for (auto &it : module->cells_)
- for (auto &conn : it.second->connections())
- if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
+ for (auto cell : module->cells())
+ for (auto &conn : cell->connections())
+ if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second);
driven_chunks.insert(sig);
for (auto &bit : sig.to_sigbit_vector())
@@ -180,9 +180,8 @@ struct SpliceWorker
SigPool selected_bits;
if (!sel_by_cell)
- for (auto &it : module->wires_)
- if (design->selected(module, it.second))
- selected_bits.add(sigmap(it.second));
+ for (auto wire : module->selected_wires())
+ selected_bits.add(sigmap(wire));
std::vector<Cell*> mod_cells = module->cells();
@@ -343,17 +342,14 @@ struct SplicePass : public Pass {
log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n");
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- if (mod_it.second->processes.size()) {
- log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+ if (module->processes.size()) {
+ log("Skipping module %s as it contains processes.\n", module->name.c_str());
continue;
}
- SpliceWorker worker(design, mod_it.second);
+ SpliceWorker worker(design, module);
worker.sel_by_cell = sel_by_cell;
worker.sel_by_wire = sel_by_wire;
worker.sel_any_bit = sel_any_bit;
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index bf693e3d4..1e7dedd70 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -141,6 +141,9 @@ struct SplitnetsPass : public Pass {
for (auto module : design->selected_modules())
{
+ if (module->has_processes_warn())
+ continue;
+
SplitnetsWorker worker;
if (flag_ports)
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 758a59661..6c4bc0e5b 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -79,18 +79,15 @@ struct statdata_t
STAT_NUMERIC_MEMBERS
#undef X
- for (auto &it : mod->wires_)
+ for (auto wire : mod->selected_wires())
{
- if (!design->selected(mod, it.second))
- continue;
-
- if (it.first[0] == '\\') {
+ if (wire->name[0] == '\\') {
num_pub_wires++;
- num_pub_wire_bits += it.second->width;
+ num_pub_wire_bits += wire->width;
}
num_wires++;
- num_wire_bits += it.second->width;
+ num_wire_bits += wire->width;
}
for (auto &it : mod->memories) {
@@ -100,12 +97,9 @@ struct statdata_t
num_memory_bits += it.second->width * it.second->size;
}
- for (auto &it : mod->cells_)
+ for (auto cell : mod->selected_cells())
{
- if (!design->selected(mod, it.second))
- continue;
-
- RTLIL::IdString cell_type = it.second->type;
+ RTLIL::IdString cell_type = cell->type;
if (width_mode)
{
@@ -116,15 +110,15 @@ struct statdata_t
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) {
- int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
- int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
- int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
+ int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
+ int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
+ int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in(ID($mux), ID($pmux)))
- cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
- cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Q)));
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
}
if (!cell_area.empty()) {
@@ -157,7 +151,7 @@ struct statdata_t
log(" Number of cells: %6d\n", num_cells);
for (auto &it : num_cells_by_type)
if (it.second)
- log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
+ log(" %-26s %6d\n", log_id(it.first), it.second);
if (!unknown_cell_area.empty()) {
log("\n");
@@ -255,7 +249,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
for (auto &it : num_cells_by_type)
if (mod_stat.count(it.first) > 0) {
- log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
+ log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, log_id(it.first), it.second);
mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
mod_data.num_cells -= it.second;
} else {
@@ -281,7 +275,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
continue;
LibertyAst *ar = cell->find("area");
- if (ar != NULL && !ar->value.empty())
+ if (ar != nullptr && !ar->value.empty())
cell_area["\\" + cell->args[0]] = atof(ar->value.c_str());
}
}
@@ -319,7 +313,7 @@ struct StatPass : public Pass {
log_header(design, "Printing statistics.\n");
bool width_mode = false;
- RTLIL::Module *top_mod = NULL;
+ RTLIL::Module *top_mod = nullptr;
std::map<RTLIL::IdString, statdata_t> mod_stat;
dict<IdString, double> cell_area;
string techname;
@@ -342,9 +336,9 @@ struct StatPass : public Pass {
continue;
}
if (args[argidx] == "-top" && argidx+1 < args.size()) {
- if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0)
+ if (design->module(RTLIL::escape_id(args[argidx+1])) == nullptr)
log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
- top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx]));
+ top_mod = design->module(RTLIL::escape_id(args[++argidx]));
continue;
}
break;
@@ -364,18 +358,18 @@ struct StatPass : public Pass {
mod_stat[mod->name] = data;
log("\n");
- log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
+ log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
log("\n");
data.log_data(mod->name, false);
}
- if (top_mod != NULL && GetSize(mod_stat) > 1)
+ if (top_mod != nullptr && GetSize(mod_stat) > 1)
{
log("\n");
log("=== design hierarchy ===\n");
log("\n");
- log(" %-28s %6d\n", RTLIL::id2cstr(top_mod->name), 1);
+ log(" %-28s %6d\n", log_id(top_mod->name), 1);
statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0);
log("\n");
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-25 04:06:10 +0000