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-rw-r--r--passes/cmds/design.cc3
-rw-r--r--passes/cmds/exec.cc2
2 files changed, 4 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 172addcc1..fab23fc1d 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -18,6 +18,7 @@
*/
#include "kernel/yosys.h"
+#include "frontends/verilog/preproc.h"
#include "frontends/ast/ast.h"
YOSYS_NAMESPACE_BEGIN
@@ -346,7 +347,7 @@ struct DesignPass : public Pass {
delete node;
design->verilog_globals.clear();
- design->verilog_defines.clear();
+ design->verilog_defines->clear();
}
if (!load_name.empty() || pop_mode)
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index 399cb0ebb..7eeefe705 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -22,11 +22,13 @@
#include <cstdio>
#if defined(_WIN32)
+# include <csignal>
# define WIFEXITED(x) 1
# define WIFSIGNALED(x) 0
# define WIFSTOPPED(x) 0
# define WEXITSTATUS(x) ((x) & 0xff)
# define WTERMSIG(x) SIGTERM
+# define WSTOPSIG(x) 0
#else
# include <sys/wait.h>
#endif