diff options
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/design.cc | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 4612760cc..3b97819e3 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -99,6 +99,11 @@ struct DesignPass : public Pass { log("The Verilog front-end remembers defined macros and top-level declarations\n"); log("between calls to 'read_verilog'. This command resets this memory.\n"); log("\n"); + log(" design -delete <name>\n"); + log("\n"); + log("Delete the design previously saved under the given name.\n"); + log("\n"); + } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -110,7 +115,7 @@ struct DesignPass : public Pass { bool pop_mode = false; bool import_mode = false; RTLIL::Design *copy_from_design = NULL, *copy_to_design = NULL; - std::string save_name, load_name, as_name; + std::string save_name, load_name, as_name, delete_name; std::vector<RTLIL::Module*> copy_src_modules; size_t argidx; @@ -190,6 +195,13 @@ struct DesignPass : public Pass { as_name = args[++argidx]; continue; } + if (!got_mode && args[argidx] == "-delete" && argidx+1 < args.size()) { + got_mode = true; + delete_name = args[++argidx]; + if (saved_designs.count(delete_name) == 0) + log_cmd_error("No saved design '%s' found!\n", delete_name.c_str()); + continue; + } break; } @@ -379,6 +391,14 @@ struct DesignPass : public Pass { pushed_designs.pop_back(); } } + + if (!delete_name.empty()) + { + auto it = saved_designs.find(delete_name); + log_assert(it != saved_designs.end()); + delete it->second; + saved_designs.erase(it); + } } } DesignPass; |