3 files changed, 48 insertions, 15 deletions

diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index ad6a07fa0..a75927393 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -133,6 +133,7 @@ struct BugpointPass : public Pass {
 		int index = 0;
 		if (modules)
 		{
+			Module *removed_module = nullptr;
 			for (auto module : design_copy->modules())
 			{
 				if (module->get_blackbox_attribute())
@@ -141,10 +142,14 @@ struct BugpointPass : public Pass {
 				if (index++ == seed)
 				{
 					log("Trying to remove module %s.\n", module->name.c_str());
-					design_copy->remove(module);
-					return design_copy;
+					removed_module = module;
+					break;
 				}
 			}
+			if (removed_module) {
+				design_copy->remove(removed_module);
+				return design_copy;
+			}
 		}
 		if (ports)
 		{
@@ -178,15 +183,20 @@ struct BugpointPass : public Pass {
 				if (mod->get_blackbox_attribute())
 					continue;
 
+				Cell *removed_cell = nullptr;
 				for (auto cell : mod->cells())
 				{
 					if (index++ == seed)
 					{
 						log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str());
-						mod->remove(cell);
-						return design_copy;
+						removed_cell = cell;
+						break;
 					}
 				}
+				if (removed_cell) {
+					mod->remove(removed_cell);
+					return design_copy;
+				}
 			}
 		}
 		if (connections)
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index cfe97067d..421defe0c 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -228,14 +228,20 @@ struct DesignPass : public Pass {
 			}
 
 			if (import_mode) {
+				std::vector<RTLIL::Module*> candidates;
 				for (auto module : copy_src_modules)
 				{
 					if (module->get_bool_attribute(ID::top)) {
-						copy_src_modules.clear();
-						copy_src_modules.push_back(module);
+						candidates.clear();
+						candidates.push_back(module);
 						break;
 					}
+					if (!module->get_blackbox_attribute())
+						candidates.push_back(module);
 				}
+
+				if (GetSize(candidates) == 1)
+					copy_src_modules = std::move(candidates);
 			}
 		}
 
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index c04ff438a..6e728c16f 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -630,8 +630,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 	std::string arg_mod, arg_memb;
 	std::unordered_map<std::string, bool> arg_mod_found;
 	std::unordered_map<std::string, bool> arg_memb_found;
-	auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); };
-	bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':';
+
+	auto isprefixed = [](const string &s) {
+		return GetSize(s) >= 2 && ((s[0] >= 'a' && s[0] <= 'z') || (s[0] >= 'A' && s[0] <= 'Z')) && s[1] == ':';
+	};
 
 	if (arg.size() == 0)
 		return;
@@ -759,31 +761,40 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 		return;
 	}
 
+	bool select_blackboxes = false;
+	if (arg.substr(0, 1) == "=") {
+		arg = arg.substr(1);
+		select_blackboxes = true;
+	}
+
 	if (!design->selected_active_module.empty()) {
 		arg_mod = design->selected_active_module;
 		arg_memb = arg;
-		if (!prefixed) arg_memb_found[arg_memb] = false;
+		if (!isprefixed(arg_memb))
+			arg_memb_found[arg_memb] = false;
 	} else
-	if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') {
+	if (isprefixed(arg) && arg[0] >= 'a' && arg[0] <= 'z') {
 		arg_mod = "*", arg_memb = arg;
 	} else {
 		size_t pos = arg.find('/');
 		if (pos == std::string::npos) {
 			arg_mod = arg;
-			if (!prefixed) arg_mod_found[arg_mod] = false;
+			if (!isprefixed(arg_mod))
+				arg_mod_found[arg_mod] = false;
 		} else {
 			arg_mod = arg.substr(0, pos);
-			if (!prefixed) arg_mod_found[arg_mod] = false;
+			if (!isprefixed(arg_mod))
+				arg_mod_found[arg_mod] = false;
 			arg_memb = arg.substr(pos+1);
-			bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':';
-			if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false;
+			if (!isprefixed(arg_memb))
+				arg_memb_found[arg_memb] = false;
 		}
 	}
 
 	work_stack.push_back(RTLIL::Selection());
 	RTLIL::Selection &sel = work_stack.back();
 
-	if (arg == "*" && arg_mod == "*") {
+	if (arg == "*" && arg_mod == "*" && select_blackboxes) {
 		select_filter_active_mod(design, work_stack.back());
 		return;
 	}
@@ -791,6 +802,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 	sel.full_selection = false;
 	for (auto mod : design->modules())
 	{
+		if (!select_blackboxes && mod->get_blackbox_attribute())
+			continue;
+
 		if (arg_mod.compare(0, 2, "A:") == 0) {
 			if (!match_attr(mod->attributes, arg_mod.substr(2)))
 				continue;
@@ -1104,6 +1118,9 @@ struct SelectPass : public Pass {
 		log("    <obj_pattern>\n");
 		log("        select the specified object(s) from the current module\n");
 		log("\n");
+		log("By default, patterns will not match black/white-box modules or their");
+		log("contents. To include such objects, prefix the pattern with '='.\n");
+		log("\n");
 		log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
 		log("matching module names, or one of the following:\n");
 		log("\n");