5 files changed, 89 insertions, 42 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 60f20fa6d..a88980eaf 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -1,5 +1,7 @@
 
+ifeq ($(DISABLE_SPAWN),0)
 OBJS += passes/cmds/exec.o
+endif
 OBJS += passes/cmds/add.o
 OBJS += passes/cmds/delete.o
 OBJS += passes/cmds/design.o
@@ -32,6 +34,8 @@ OBJS += passes/cmds/chformal.o
 OBJS += passes/cmds/chtype.o
 OBJS += passes/cmds/blackbox.o
 OBJS += passes/cmds/ltp.o
+ifeq ($(DISABLE_SPAWN),0)
 OBJS += passes/cmds/bugpoint.o
+endif
 OBJS += passes/cmds/scratchpad.o
 OBJS += passes/cmds/logger.o
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index a75927393..00aac596f 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -30,23 +30,21 @@ struct BugpointPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    bugpoint [options]\n");
+		log("    bugpoint [options] -script <filename>\n");
 		log("\n");
-		log("This command minimizes testcases that crash Yosys. It removes an arbitrary part\n");
-		log("of the design and recursively invokes Yosys with a given script, repeating these\n");
-		log("steps while it can find a smaller design that still causes a crash. Once this\n");
-		log("command finishes, it replaces the current design with the smallest testcase it\n");
-		log("was able to produce.\n");
+		log("This command minimizes the current design that is known to crash Yosys with the\n");
+		log("given script into a smaller testcase. It does this by removing an arbitrary part\n");
+		log("of the design and recursively invokes a new Yosys process with this modified design\n");
+		log("and the same script, repeating these steps while it can find a smaller design that\n");
+		log("still causes a crash. Once this command finishes, it replaces the current design\n");
+		log("with the smallest testcase it was able to produce.\n");
 		log("\n");
-		log("It is possible to specify the kinds of design part that will be removed. If none\n");
-		log("are specified, all parts of design will be removed.\n");
+		log("    -script <filename>\n");
+		log("        use this script to crash Yosys. required.\n");
 		log("\n");
 		log("    -yosys <filename>\n");
 		log("        use this Yosys binary. if not specified, `yosys` is used.\n");
 		log("\n");
-		log("    -script <filename>\n");
-		log("        use this script to crash Yosys. required.\n");
-		log("\n");
 		log("    -grep <string>\n");
 		log("        only consider crashes that place this string in the log file.\n");
 		log("\n");
@@ -60,14 +58,21 @@ struct BugpointPass : public Pass {
 		log("        finishing. produces smaller and more useful testcases, but may fail to\n");
 		log("        produce any testcase at all if the crash is related to dangling wires.\n");
 		log("\n");
+		log("It is possible to constrain which parts of the design will be considered for\n");
+		log("removal. Unless one or more of the following options are specified, all parts\n");
+		log("will be considered.\n");
+		log("\n");
 		log("    -modules\n");
-		log("        try to remove modules.\n");
+		log("        try to remove modules. modules with a (* bugpoint_keep *) attribute\n");
+		log("        will be skipped.\n");
 		log("\n");
 		log("    -ports\n");
-		log("        try to remove module ports.\n");
+		log("        try to remove module ports. ports with a (* bugpoint_keep *) attribute\n");
+		log("        will be skipped (useful for clocks, resets, etc.)\n");
 		log("\n");
 		log("    -cells\n");
-		log("        try to remove cells.\n");
+		log("        try to remove cells. cells with a (* bugpoint_keep *) attribute will\n");
+		log("        be skipped.\n");
 		log("\n");
 		log("    -connections\n");
 		log("        try to reconnect ports to 'x.\n");
@@ -139,9 +144,12 @@ struct BugpointPass : public Pass {
 				if (module->get_blackbox_attribute())
 					continue;
 
+				if (module->get_bool_attribute(ID::bugpoint_keep))
+				    continue;
+
 				if (index++ == seed)
 				{
-					log("Trying to remove module %s.\n", module->name.c_str());
+					log_header(design, "Trying to remove module %s.\n", log_id(module));
 					removed_module = module;
 					break;
 				}
@@ -160,18 +168,21 @@ struct BugpointPass : public Pass {
 
 				for (auto wire : mod->wires())
 				{
+					if (!wire->port_id)
+						continue;
+
 					if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
 						continue;
 
-					if (wire->port_input || wire->port_output)
+					if (wire->get_bool_attribute(ID::bugpoint_keep))
+						continue;
+
+					if (index++ == seed)
 					{
-						if (index++ == seed)
-						{
-							log("Trying to remove module port %s.\n", log_signal(wire));
-							wire->port_input = wire->port_output = false;
-							mod->fixup_ports();
-							return design_copy;
-						}
+						log_header(design, "Trying to remove module port %s.\n", log_id(wire));
+						wire->port_input = wire->port_output = false;
+						mod->fixup_ports();
+						return design_copy;
 					}
 				}
 			}
@@ -183,12 +194,16 @@ struct BugpointPass : public Pass {
 				if (mod->get_blackbox_attribute())
 					continue;
 
+
 				Cell *removed_cell = nullptr;
 				for (auto cell : mod->cells())
 				{
+					if (cell->get_bool_attribute(ID::bugpoint_keep))
+						continue;
+
 					if (index++ == seed)
 					{
-						log("Trying to remove cell %s.%s.\n", mod->name.c_str(), cell->name.c_str());
+						log_header(design, "Trying to remove cell %s.%s.\n", log_id(mod), log_id(cell));
 						removed_cell = cell;
 						break;
 					}
@@ -219,7 +234,7 @@ struct BugpointPass : public Pass {
 
 						if (index++ == seed)
 						{
-							log("Trying to remove cell port %s.%s.%s.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
+							log_header(design, "Trying to remove cell port %s.%s.%s.\n", log_id(mod), log_id(cell), log_id(it.first));
 							RTLIL::SigSpec port_x(State::Sx, port.size());
 							cell->unsetPort(it.first);
 							cell->setPort(it.first, port_x);
@@ -228,7 +243,7 @@ struct BugpointPass : public Pass {
 
 						if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
 						{
-							log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
+							log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", log_id(mod), log_id(cell), log_id(it.first));
 							RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
 							wire->set_bool_attribute(ID($bugpoint));
 							wire->port_input = cell->input(it.first);
@@ -260,7 +275,7 @@ struct BugpointPass : public Pass {
 						{
 							if (index++ == seed)
 							{
-								log("Trying to remove assign %s %s in %s.%s.\n", log_signal((*it).first), log_signal((*it).second), mod->name.c_str(), pr.first.c_str());
+								log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
 								cs->actions.erase(it);
 								return design_copy;
 							}
@@ -286,7 +301,7 @@ struct BugpointPass : public Pass {
 						{
 							if (index++ == seed)
 							{
-								log("Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal((*it).first), log_signal((*it).second), mod->name.c_str(), pr.first.c_str());
+								log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), log_id(mod), log_id(pr.first));
 								sy->actions.erase(it);
 								return design_copy;
 							}
@@ -304,6 +319,9 @@ struct BugpointPass : public Pass {
 		bool fast = false, clean = false;
 		bool modules = false, ports = false, cells = false, connections = false, assigns = false, updates = false, has_part = false;
 
+		log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
+		log_push();
+
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -447,6 +465,8 @@ struct BugpointPass : public Pass {
 				design->add(module->clone());
 			delete crashing_design;
 		}
+
+		log_pop();
 	}
 } BugpointPass;
 
diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc
index 628ac4c5e..89d27c9aa 100644
--- a/passes/cmds/cover.cc
+++ b/passes/cmds/cover.cc
@@ -101,8 +101,8 @@ struct CoverPass : public Pass {
 				const std::string &filename = args[++argidx];
 				FILE *f = nullptr;
 				if (args[argidx-1] == "-d") {
-			#ifdef _WIN32
-					log_cmd_error("The 'cover -d' option is not supported on win32.\n");
+			#if defined(_WIN32) || defined(__wasm)
+					log_cmd_error("The 'cover -d' option is not supported on this platform.\n");
 			#else
 					char filename_buffer[4096];
 					snprintf(filename_buffer, 4096, "%s/yosys_cover_%d_XXXXXX.txt", filename.c_str(), getpid());
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index c04ff438a..6e728c16f 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -630,8 +630,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 	std::string arg_mod, arg_memb;
 	std::unordered_map<std::string, bool> arg_mod_found;
 	std::unordered_map<std::string, bool> arg_memb_found;
-	auto isalpha = [](const char &x) { return ((x >= 'a' && x <= 'z') || (x >= 'A' && x <= 'Z')); };
-	bool prefixed = GetSize(arg) >= 2 && isalpha(arg[0]) && arg[1] == ':';
+
+	auto isprefixed = [](const string &s) {
+		return GetSize(s) >= 2 && ((s[0] >= 'a' && s[0] <= 'z') || (s[0] >= 'A' && s[0] <= 'Z')) && s[1] == ':';
+	};
 
 	if (arg.size() == 0)
 		return;
@@ -759,31 +761,40 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 		return;
 	}
 
+	bool select_blackboxes = false;
+	if (arg.substr(0, 1) == "=") {
+		arg = arg.substr(1);
+		select_blackboxes = true;
+	}
+
 	if (!design->selected_active_module.empty()) {
 		arg_mod = design->selected_active_module;
 		arg_memb = arg;
-		if (!prefixed) arg_memb_found[arg_memb] = false;
+		if (!isprefixed(arg_memb))
+			arg_memb_found[arg_memb] = false;
 	} else
-	if (prefixed && arg[0] >= 'a' && arg[0] <= 'z') {
+	if (isprefixed(arg) && arg[0] >= 'a' && arg[0] <= 'z') {
 		arg_mod = "*", arg_memb = arg;
 	} else {
 		size_t pos = arg.find('/');
 		if (pos == std::string::npos) {
 			arg_mod = arg;
-			if (!prefixed) arg_mod_found[arg_mod] = false;
+			if (!isprefixed(arg_mod))
+				arg_mod_found[arg_mod] = false;
 		} else {
 			arg_mod = arg.substr(0, pos);
-			if (!prefixed) arg_mod_found[arg_mod] = false;
+			if (!isprefixed(arg_mod))
+				arg_mod_found[arg_mod] = false;
 			arg_memb = arg.substr(pos+1);
-			bool arg_memb_prefixed = GetSize(arg_memb) >= 2 && isalpha(arg_memb[0]) && arg_memb[1] == ':';
-			if (!arg_memb_prefixed) arg_memb_found[arg_memb] = false;
+			if (!isprefixed(arg_memb))
+				arg_memb_found[arg_memb] = false;
 		}
 	}
 
 	work_stack.push_back(RTLIL::Selection());
 	RTLIL::Selection &sel = work_stack.back();
 
-	if (arg == "*" && arg_mod == "*") {
+	if (arg == "*" && arg_mod == "*" && select_blackboxes) {
 		select_filter_active_mod(design, work_stack.back());
 		return;
 	}
@@ -791,6 +802,9 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
 	sel.full_selection = false;
 	for (auto mod : design->modules())
 	{
+		if (!select_blackboxes && mod->get_blackbox_attribute())
+			continue;
+
 		if (arg_mod.compare(0, 2, "A:") == 0) {
 			if (!match_attr(mod->attributes, arg_mod.substr(2)))
 				continue;
@@ -1104,6 +1118,9 @@ struct SelectPass : public Pass {
 		log("    <obj_pattern>\n");
 		log("        select the specified object(s) from the current module\n");
 		log("\n");
+		log("By default, patterns will not match black/white-box modules or their");
+		log("contents. To include such objects, prefix the pattern with '='.\n");
+		log("\n");
 		log("A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])\n");
 		log("matching module names, or one of the following:\n");
 		log("\n");
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 155ed0fcd..fa922454a 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -682,7 +682,7 @@ struct ShowPass : public Pass {
 		std::vector<std::pair<std::string, RTLIL::Selection>> color_selections;
 		std::vector<std::pair<std::string, RTLIL::Selection>> label_selections;
 
-#if defined(EMSCRIPTEN) || defined(_WIN32)
+#if defined(_WIN32) || defined(YOSYS_DISABLE_SPAWN)
 		std::string format = "dot";
 		std::string prefix = "show";
 #else
@@ -849,10 +849,15 @@ struct ShowPass : public Pass {
 			std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
 			#undef DOT_CMD
 			log("Exec: %s\n", cmd.c_str());
-			if (run_command(cmd) != 0)
-				log_cmd_error("Shell command failed!\n");
+			#if !defined(YOSYS_DISABLE_SPAWN)
+				if (run_command(cmd) != 0)
+					log_cmd_error("Shell command failed!\n");
+			#endif
 		}
 
+		#if defined(YOSYS_DISABLE_SPAWN)
+			log_assert(viewer_exe.empty() && !format.empty());
+		#else
 		if (!viewer_exe.empty()) {
 			#ifdef _WIN32
 				// system()/cmd.exe does not understand single quotes nor
@@ -876,6 +881,7 @@ struct ShowPass : public Pass {
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");
 		}
+		#endif
 
 		if (flag_pause) {
 		#ifdef YOSYS_ENABLE_READLINE