diff options
Diffstat (limited to 'passes/equiv/equiv_make.cc')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 50572ae5c..6923ae3d0 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -114,25 +114,25 @@ struct EquivMakeWorker Module *gate_clone = gate_mod->clone(); for (auto it : gold_clone->wires().to_vector()) { - if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0) + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) wire_names.insert(it->name); gold_clone->rename(it, it->name.str() + "_gold"); } for (auto it : gold_clone->cells().to_vector()) { - if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0) + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); gold_clone->rename(it, it->name.str() + "_gold"); } for (auto it : gate_clone->wires().to_vector()) { - if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0) + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) wire_names.insert(it->name); gate_clone->rename(it, it->name.str() + "_gate"); } for (auto it : gate_clone->cells().to_vector()) { - if ((it->name[0] == '\\' || inames) && blacklist_names.count(it->name) == 0) + if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); gate_clone->rename(it, it->name.str() + "_gate"); } @@ -466,7 +466,7 @@ struct EquivMakeWorker struct EquivMakePass : public Pass { EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -491,7 +491,7 @@ struct EquivMakePass : public Pass { log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { EquivMakeWorker worker; worker.ct.setup(design); |