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-rw-r--r--passes/equiv/equiv_purge.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 18b3e7d36..688c20f43 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -102,7 +102,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
{
- if (cell->type != "$equiv") {
+ if (cell->type != ID($equiv)) {
for (auto &port : cell->connections()) {
if (cell->input(port.first))
for (auto bit : sigmap(port.second))
@@ -114,9 +114,9 @@ struct EquivPurgeWorker
continue;
}
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_y = sigmap(cell->getPort(ID::Y));
if (sig_a == sig_b)
continue;
@@ -130,7 +130,7 @@ struct EquivPurgeWorker
for (auto bit : sig_y)
visited.insert(bit);
- cell->setPort("\\Y", make_output(sig_y, cell->name));
+ cell->setPort(ID::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
@@ -167,8 +167,8 @@ struct EquivPurgeWorker
rewrite_sigmap.add(chunk, make_input(chunk));
for (auto cell : module->cells())
- if (cell->type == "$equiv")
- cell->setPort("\\Y", rewrite_sigmap(sigmap(cell->getPort("\\Y"))));
+ if (cell->type == ID($equiv))
+ cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports();
}