1 files changed, 23 insertions, 23 deletions

diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 68222769a..47398b558 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -33,31 +33,31 @@ struct FsmData
 
 	void copy_to_cell(RTLIL::Cell *cell)
 	{
-		cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs);
-		cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs);
+		cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);
+		cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);
 
 		int state_num_log2 = 0;
 		for (int i = state_table.size(); i > 0; i = i >> 1)
 			state_num_log2++;
 		state_num_log2 = max(state_num_log2, 1);
 
-		cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
-		cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
-		cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2);
-		cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state);
-		cell->parameters["\\STATE_TABLE"] = RTLIL::Const();
+		cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);
+		cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
+		cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
+		cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
+		cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
 
 		for (int i = 0; i < int(state_table.size()); i++) {
-			std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits;
+			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
 			std::vector<RTLIL::State> &bits_state = state_table[i].bits;
 			bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
 		}
 
-		cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size());
-		cell->parameters["\\TRANS_TABLE"] = RTLIL::Const();
+		cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
+		cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
 		for (int i = 0; i < int(transition_table.size()); i++)
 		{
-			std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits;
+			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
 			transition_t &tr = transition_table[i];
 
 			RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
@@ -78,21 +78,21 @@ struct FsmData
 
 	void copy_from_cell(RTLIL::Cell *cell)
 	{
-		num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int();
-		num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int();
+		num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();
+		num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();
 
-		state_bits = cell->parameters["\\STATE_BITS"].as_int();
-		reset_state = cell->parameters["\\STATE_RST"].as_int();
+		state_bits = cell->parameters[ID::STATE_BITS].as_int();
+		reset_state = cell->parameters[ID::STATE_RST].as_int();
 
-		int state_num = cell->parameters["\\STATE_NUM"].as_int();
-		int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int();
-		int trans_num = cell->parameters["\\TRANS_NUM"].as_int();
+		int state_num = cell->parameters[ID::STATE_NUM].as_int();
+		int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();
+		int trans_num = cell->parameters[ID::TRANS_NUM].as_int();
 
 		if (reset_state < 0 || reset_state >= state_num)
 			reset_state = -1;
 
-		RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"];
-		RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"];
+		RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
+		RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
 
 		for (int i = 0; i < state_num; i++) {
 			RTLIL::Const state_code;
@@ -134,7 +134,7 @@ struct FsmData
 	{
 		log("-------------------------------------\n");
 		log("\n");
-		log("  Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
+		log("  Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
 		log("\n");
 		log("  Number of input signals:  %3d\n", num_inputs);
 		log("  Number of output signals: %3d\n", num_outputs);
@@ -142,13 +142,13 @@ struct FsmData
 
 		log("\n");
 		log("  Input signals:\n");
-		RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
+		RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
 		for (int i = 0; i < GetSize(sig_in); i++)
 			log("  %3d: %s\n", i, log_signal(sig_in[i]));
 
 		log("\n");
 		log("  Output signals:\n");
-		RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
+		RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
 		for (int i = 0; i < GetSize(sig_out); i++)
 			log("  %3d: %s\n", i, log_signal(sig_out[i]));