diff options
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 18 | ||||
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 60 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 36 | ||||
| -rw-r--r-- | passes/fsm/fsm_map.cc | 56 | ||||
| -rw-r--r-- | passes/fsm/fsm_opt.cc | 14 | ||||
| -rw-r--r-- | passes/fsm/fsmdata.h | 4 |
6 files changed, 98 insertions, 90 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e59676599..be851afa6 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig for (auto &cellport : cellport_list) { if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y") return false; - RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]); + RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B")); if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor)) return false; for (int i = 0; i < sig_b.size(); i += sig_a.size()) @@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0) + if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0) return false; - for (auto &port_it : cell->connections_) + for (auto &port_it : cell->connections()) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") return false; - if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const()) + if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const()) continue; - if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const()) + if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const()) continue; return false; } @@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire) continue; muxtree_cells.clear(); SigPool recursion_monitor; - RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]); + RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D")); if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) { log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str()); wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto"); @@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass { sig2user.clear(); sig_at_port.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections_) { + for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 431f086d2..ed80d7c31 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -43,34 +43,34 @@ struct FsmExpand bool is_cell_merge_candidate(RTLIL::Cell *cell) { if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") - if (cell->connections_.at("\\A").size() < 2) + if (cell->get("\\A").size() < 2) return true; RTLIL::SigSpec new_signals; - if (cell->connections_.count("\\A") > 0) - new_signals.append(assign_map(cell->connections_["\\A"])); - if (cell->connections_.count("\\B") > 0) - new_signals.append(assign_map(cell->connections_["\\B"])); - if (cell->connections_.count("\\S") > 0) - new_signals.append(assign_map(cell->connections_["\\S"])); - if (cell->connections_.count("\\Y") > 0) - new_signals.append(assign_map(cell->connections_["\\Y"])); + if (cell->connections().count("\\A") > 0) + new_signals.append(assign_map(cell->get("\\A"))); + if (cell->connections().count("\\B") > 0) + new_signals.append(assign_map(cell->get("\\B"))); + if (cell->connections().count("\\S") > 0) + new_signals.append(assign_map(cell->get("\\S"))); + if (cell->connections().count("\\Y") > 0) + new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); if (new_signals.size() > 3) return false; - if (cell->connections_.count("\\Y") > 0) { - new_signals.append(assign_map(cell->connections_["\\Y"])); + if (cell->connections().count("\\Y") > 0) { + new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"])); - new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"])); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN"))); + new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT"))); } if (new_signals.size() > 2) @@ -83,10 +83,10 @@ struct FsmExpand { std::vector<RTLIL::Cell*> cell_list; - for (auto c : sig2driver.find(assign_map(fsm_cell->connections_["\\CTRL_IN"]))) + for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN")))) cell_list.push_back(c); - for (auto c : sig2user.find(assign_map(fsm_cell->connections_["\\CTRL_OUT"]))) + for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT")))) cell_list.push_back(c); current_set.clear(); @@ -94,7 +94,7 @@ struct FsmExpand { if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; - for (auto &p : c->connections_) { + for (auto &p : c->connections()) { if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y") goto next_cell; } @@ -135,7 +135,7 @@ struct FsmExpand RTLIL::SigSpec input_sig, output_sig; - for (auto &p : cell->connections_) + for (auto &p : cell->connections()) if (ct.cell_output(cell->type, p.first)) output_sig.append(assign_map(p.second)); else @@ -148,12 +148,12 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->connections_.count("\\A") > 0) - A = assign_map(cell->connections_["\\A"]); - if (cell->connections_.count("\\B") > 0) - B = assign_map(cell->connections_["\\B"]); - if (cell->connections_.count("\\S") > 0) - S = assign_map(cell->connections_["\\S"]); + if (cell->connections().count("\\A") > 0) + A = assign_map(cell->get("\\A")); + if (cell->connections().count("\\B") > 0) + B = assign_map(cell->get("\\B")); + if (cell->connections().count("\\S") > 0) + S = assign_map(cell->get("\\S")); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); S.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -167,10 +167,14 @@ struct FsmExpand fsm_data.copy_from_cell(fsm_cell); fsm_data.num_inputs += input_sig.size(); - fsm_cell->connections_["\\CTRL_IN"].append(input_sig); + RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN"); + new_ctrl_in.append(input_sig); + fsm_cell->set("\\CTRL_IN", new_ctrl_in); fsm_data.num_outputs += output_sig.size(); - fsm_cell->connections_["\\CTRL_OUT"].append(output_sig); + RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT"); + new_ctrl_out.append(output_sig); + fsm_cell->set("\\CTRL_OUT", new_ctrl_out); std::vector<FsmData::transition_t> new_transition_table; for (auto &tr : fsm_data.transition_table) { @@ -204,7 +208,7 @@ struct FsmExpand for (auto &cell_it : module->cells) { RTLIL::Cell *c = cell_it.second; if (ct.cell_known(c->type) && design->selected(mod, c)) - for (auto &p : c->connections_) { + for (auto &p : c->connections()) { if (ct.cell_output(c->type, p.first)) sig2driver.insert(assign_map(p.second), c); else diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index b0e1c903b..e89bba893 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; } - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_s = assign_map(cell->get("\\S")); if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { if (sig_a.is_fully_def()) @@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire) if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); - RTLIL::SigSpec sig_q = assign_map(cell->connections_["\\Q"]); - RTLIL::SigSpec sig_d = assign_map(cell->connections_["\\D"]); - clk = cell->connections_["\\CLK"]; + RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q")); + RTLIL::SigSpec sig_d = assign_map(cell->get("\\D")); + clk = cell->get("\\CLK"); clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - arst = cell->connections_["\\ARST"]; + arst = cell->get("\\ARST"); arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); reset_state = cell->parameters["\\ARST_VALUE"]; } @@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire) sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]); - RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]); - RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]); + RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); + RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; if (cellport.second == "\\B" && !sig_a.is_fully_const()) @@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm"); - fsm_cell->connections_["\\CLK"] = clk; - fsm_cell->connections_["\\ARST"] = arst; + fsm_cell->set("\\CLK", clk); + fsm_cell->set("\\ARST", arst); fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1); fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1); - fsm_cell->connections_["\\CTRL_IN"] = ctrl_in; - fsm_cell->connections_["\\CTRL_OUT"] = ctrl_out; + fsm_cell->set("\\CTRL_IN", ctrl_in); + fsm_cell->set("\\CTRL_OUT", ctrl_out); fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name); fsm_cell->attributes = wire->attributes; fsm_data.copy_to_cell(fsm_cell); @@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells.at(cellport.first); - RTLIL::SigSpec port_sig = assign_map(cell->connections_[cellport.second]); + RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = new RTLIL::Wire; unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++); @@ -344,14 +344,14 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); for (auto &cell_it : module->cells) - for (auto &conn_it : cell_it.second->connections_) { + for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections_.count("\\Y") > 0 && - cell_it.second->connections_["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 && + cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index cf482d6df..a22441b4a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const and_sig.append(RTLIL::SigSpec(eq_wire)); RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->connections_["\\A"] = eq_sig_a; - eq_cell->connections_["\\B"] = eq_sig_b; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(eq_wire); + eq_cell->set("\\A", eq_sig_a); + eq_cell->set("\\B", eq_sig_b); + eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); @@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const and_sig.append(RTLIL::SigSpec(or_wire)); RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->connections_["\\A"] = or_sig; - or_cell->connections_["\\Y"] = RTLIL::SigSpec(or_wire); + or_cell->set("\\A", or_sig); + or_cell->set("\\Y", RTLIL::SigSpec(or_wire)); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); @@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const cases_vector.append(RTLIL::SigSpec(and_wire)); RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and"); - and_cell->connections_["\\A"] = and_sig.extract(0, 1); - and_cell->connections_["\\B"] = and_sig.extract(1, 1); - and_cell->connections_["\\Y"] = RTLIL::SigSpec(and_wire); + and_cell->set("\\A", and_sig.extract(0, 1)); + and_cell->set("\\B", and_sig.extract(1, 1)); + and_cell->set("\\Y", RTLIL::SigSpec(and_wire)); and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); @@ -119,15 +119,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const if (cases_vector.size() > 1) { RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); - or_cell->connections_["\\A"] = cases_vector; - or_cell->connections_["\\Y"] = output; + or_cell->set("\\A", cases_vector); + or_cell->set("\\Y", output); or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); } else if (cases_vector.size() == 1) { - module->connections_.push_back(RTLIL::SigSig(output, cases_vector)); + module->connect(RTLIL::SigSig(output, cases_vector)); } else { - module->connections_.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); + module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1))); } } @@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); - RTLIL::SigSpec ctrl_in = fsm_cell->connections_["\\CTRL_IN"]; - RTLIL::SigSpec ctrl_out = fsm_cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN"); + RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT"); // create state register @@ -153,7 +153,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); - if (fsm_cell->connections_["\\ARST"].is_fully_const()) { + if (fsm_cell->get("\\ARST").is_fully_const()) { state_dff->type = "$dff"; } else { state_dff->type = "$adff"; @@ -162,13 +162,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; - state_dff->connections_["\\ARST"] = fsm_cell->connections_["\\ARST"]; + state_dff->set("\\ARST", fsm_cell->get("\\ARST")); } state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; - state_dff->connections_["\\CLK"] = fsm_cell->connections_["\\CLK"]; - state_dff->connections_["\\D"] = RTLIL::SigSpec(next_state_wire); - state_dff->connections_["\\Q"] = RTLIL::SigSpec(state_wire); + state_dff->set("\\CLK", fsm_cell->get("\\CLK")); + state_dff->set("\\D", RTLIL::SigSpec(next_state_wire)); + state_dff->set("\\Q", RTLIL::SigSpec(state_wire)); // decode state register @@ -189,16 +189,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) if (sig_b == RTLIL::SigSpec(RTLIL::State::S1)) { - module->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); + module->connect(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a)); } else { encoding_is_onehot = false; RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); - eq_cell->connections_["\\A"] = sig_a; - eq_cell->connections_["\\B"] = sig_b; - eq_cell->connections_["\\Y"] = RTLIL::SigSpec(state_onehot, i); + eq_cell->set("\\A", sig_a); + eq_cell->set("\\B", sig_b); + eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i)); eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); @@ -245,7 +245,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i)); } log_assert(!next_state_sig.has_marked_bits()); - module->connections_.push_back(RTLIL::SigSig(next_state_wire, next_state_sig)); + module->connect(RTLIL::SigSig(next_state_wire, next_state_sig)); } else { @@ -265,10 +265,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux"); - mux_cell->connections_["\\A"] = sig_a; - mux_cell->connections_["\\B"] = sig_b; - mux_cell->connections_["\\S"] = sig_s; - mux_cell->connections_["\\Y"] = RTLIL::SigSpec(next_state_wire); + mux_cell->set("\\A", sig_a); + mux_cell->set("\\B", sig_b); + mux_cell->set("\\S", sig_s); + mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire)); mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); } diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 3fde534da..1441378a0 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -52,7 +52,7 @@ struct FsmOpt void opt_const_and_unused_inputs() { - RTLIL::SigSpec ctrl_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN"); std::vector<bool> ctrl_in_used(ctrl_in.size()); std::vector<FsmData::transition_t> new_transition_table; @@ -73,13 +73,15 @@ struct FsmOpt for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { if (!ctrl_in_used[i]) { - log(" Removing unused input signal %s.\n", log_signal(cell->connections_["\\CTRL_IN"].extract(i, 1))); + log(" Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1))); for (auto &tr : new_transition_table) { RTLIL::SigSpec tmp(tr.ctrl_in); tmp.remove(i, 1); tr.ctrl_in = tmp.as_const(); } - cell->connections_["\\CTRL_IN"].remove(i, 1); + RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN"); + new_ctrl_in.remove(i, 1); + cell->set("\\CTRL_IN", new_ctrl_in); fsm_data.num_inputs--; } } @@ -91,10 +93,12 @@ struct FsmOpt void opt_unused_outputs() { for (int i = 0; i < fsm_data.num_outputs; i++) { - RTLIL::SigSpec sig = cell->connections_["\\CTRL_OUT"].extract(i, 1); + RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1); if (signal_is_unused(sig)) { log(" Removing unused output signal %s.\n", log_signal(sig)); - cell->connections_["\\CTRL_OUT"].remove(i, 1); + RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT"); + new_ctrl_out.remove(i, 1); + cell->set("\\CTRL_OUT", new_ctrl_out); for (auto &tr : fsm_data.transition_table) { RTLIL::SigSpec tmp(tr.ctrl_out); tmp.remove(i, 1); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index a336d23f7..8f0e5d621 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -141,13 +141,13 @@ struct FsmData log("\n"); log(" Input signals:\n"); - RTLIL::SigSpec sig_in = cell->connections_["\\CTRL_IN"]; + RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN"); for (int i = 0; i < SIZE(sig_in); i++) log(" %3d: %s\n", i, log_signal(sig_in[i])); log("\n"); log(" Output signals:\n"); - RTLIL::SigSpec sig_out = cell->connections_["\\CTRL_OUT"]; + RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT"); for (int i = 0; i < SIZE(sig_out); i++) log(" %3d: %s\n", i, log_signal(sig_out[i])); |