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-rw-r--r--passes/fsm/fsm_detect.cc68
-rw-r--r--passes/fsm/fsm_expand.cc76
-rw-r--r--passes/fsm/fsm_export.cc19
-rw-r--r--passes/fsm/fsm_extract.cc86
-rw-r--r--passes/fsm/fsm_info.cc19
-rw-r--r--passes/fsm/fsm_map.cc136
-rw-r--r--passes/fsm/fsm_opt.cc34
-rw-r--r--passes/fsm/fsm_recode.cc15
-rw-r--r--passes/fsm/fsmdata.h46
9 files changed, 239 insertions, 260 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index a1c8067b4..30e9e4dad 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -55,7 +55,7 @@ ret_false:
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list)
{
- if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y") {
+ if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) {
goto ret_false;
}
@@ -67,8 +67,8 @@ ret_false:
recursion_monitor.insert(cellport.first);
- RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
+ RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
+ RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
@@ -99,18 +99,18 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
- if (cell->type == "$logic_not" && assign_map(cell->getPort("\\A")) == sig)
+ if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
continue;
- if (cellport.second != "\\A" && cellport.second != "\\B")
+ if (cellport.second != ID::A && cellport.second != ID::B)
return false;
- if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
+ if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y))
return false;
for (auto &port_it : cell->connections())
- if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
+ if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
return false;
- if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
+ if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
continue;
- if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
+ if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
continue;
return false;
}
@@ -120,9 +120,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
static void detect_fsm(RTLIL::Wire *wire)
{
- bool has_fsm_encoding_attr = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() != "none";
- bool has_fsm_encoding_none = wire->attributes.count("\\fsm_encoding") > 0 && wire->attributes.at("\\fsm_encoding").decode_string() == "none";
- bool has_init_attr = wire->attributes.count("\\init") > 0;
+ bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
+ bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
+ bool has_init_attr = wire->attributes.count(ID::init) > 0;
bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
bool looks_like_state_reg = false, looks_like_good_state_reg = false;
bool is_self_resetting = false;
@@ -133,7 +133,7 @@ static void detect_fsm(RTLIL::Wire *wire)
if (wire->width <= 1) {
if (has_fsm_encoding_attr) {
log_warning("Removing fsm_encoding attribute from 1-bit net: %s.%s\n", log_id(wire->module), log_id(wire));
- wire->attributes.erase("\\fsm_encoding");
+ wire->attributes.erase(ID::fsm_encoding);
}
return;
}
@@ -143,13 +143,13 @@ static void detect_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list)
{
- if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
+ if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q)
continue;
muxtree_cells.clear();
pool<Cell*> recursion_monitor;
- RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
- RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
+ RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
+ RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire))
@@ -173,10 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false;
- if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
+ if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
set_output = true;
- if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
+ if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
clr_output = true;
if (set_output || clr_output) {
@@ -234,7 +234,7 @@ static void detect_fsm(RTLIL::Wire *wire)
if (looks_like_state_reg && looks_like_good_state_reg && !has_init_attr && !is_module_port && !is_self_resetting)
{
log("Found FSM state register %s.%s.\n", log_id(wire->module), log_id(wire));
- wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
+ wire->attributes[ID::fsm_encoding] = RTLIL::Const("auto");
}
else
if (looks_like_state_reg)
@@ -284,38 +284,34 @@ struct FsmDetectPass : public Pass {
ct.setup_stdcells();
ct.setup_stdcells_mem();
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- module = mod_it.second;
+ module = mod;
assign_map.set(module);
sig2driver.clear();
sig2user.clear();
sig_at_port.clear();
- for (auto &cell_it : module->cells_)
- for (auto &conn_it : cell_it.second->connections()) {
- if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
+ for (auto cell : module->cells())
+ for (auto &conn_it : cell->connections()) {
+ if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
}
- if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) {
+ if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
}
}
- for (auto &wire_it : module->wires_)
- if (wire_it.second->port_id != 0)
- sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
+ for (auto wire : module->wires())
+ if (wire->port_id != 0)
+ sig_at_port.add(assign_map(wire));
- for (auto &wire_it : module->wires_)
- if (design->selected(module, wire_it.second))
- detect_fsm(wire_it.second);
+ for (auto wire : module->selected_wires())
+ detect_fsm(wire);
}
assign_map.clear();
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 1610ec751..ade6c17f5 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -47,42 +47,42 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
- if (full_mode || cell->type == "$_MUX_")
+ if (full_mode || cell->type == ID($_MUX_))
return true;
- if (cell->type.in("$mux", "$pmux"))
- if (cell->getPort("\\A").size() < 2)
+ if (cell->type.in(ID($mux), ID($pmux)))
+ if (cell->getPort(ID::A).size() < 2)
return true;
int in_bits = 0;
RTLIL::SigSpec new_signals;
- if (cell->hasPort("\\A")) {
- in_bits += GetSize(cell->getPort("\\A"));
- new_signals.append(assign_map(cell->getPort("\\A")));
+ if (cell->hasPort(ID::A)) {
+ in_bits += GetSize(cell->getPort(ID::A));
+ new_signals.append(assign_map(cell->getPort(ID::A)));
}
- if (cell->hasPort("\\B")) {
- in_bits += GetSize(cell->getPort("\\B"));
- new_signals.append(assign_map(cell->getPort("\\B")));
+ if (cell->hasPort(ID::B)) {
+ in_bits += GetSize(cell->getPort(ID::B));
+ new_signals.append(assign_map(cell->getPort(ID::B)));
}
- if (cell->hasPort("\\S")) {
- in_bits += GetSize(cell->getPort("\\S"));
- new_signals.append(assign_map(cell->getPort("\\S")));
+ if (cell->hasPort(ID::S)) {
+ in_bits += GetSize(cell->getPort(ID::S));
+ new_signals.append(assign_map(cell->getPort(ID::S)));
}
if (in_bits > 8)
return false;
- if (cell->hasPort("\\Y"))
- new_signals.append(assign_map(cell->getPort("\\Y")));
+ if (cell->hasPort(ID::Y))
+ new_signals.append(assign_map(cell->getPort(ID::Y)));
new_signals.sort_and_unify();
new_signals.remove_const();
- new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
- new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
+ new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
+ new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
if (new_signals.size() > 3)
return false;
@@ -94,10 +94,10 @@ struct FsmExpand
{
std::vector<RTLIL::Cell*> cell_list;
- for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
+ for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
cell_list.push_back(c);
- for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
+ for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
cell_list.push_back(c);
current_set.clear();
@@ -106,7 +106,7 @@ struct FsmExpand
if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0)
continue;
for (auto &p : c->connections()) {
- if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y")
+ if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y)
goto next_cell;
}
if (!is_cell_merge_candidate(c)) {
@@ -123,14 +123,14 @@ struct FsmExpand
if (already_optimized)
return;
- int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
if (trans_num > limit_transitions)
{
log(" grown transition table to %d entries -> optimize.\n", trans_num);
FsmData::optimize_fsm(fsm_cell, module);
already_optimized = true;
- trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
log(" transition table size after optimizaton: %d\n", trans_num);
limit_transitions = 16 * trans_num;
}
@@ -159,12 +159,12 @@ struct FsmExpand
for (int i = 0; i < (1 << input_sig.size()); i++) {
RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
- if (cell->hasPort("\\A"))
- A = assign_map(cell->getPort("\\A"));
- if (cell->hasPort("\\B"))
- B = assign_map(cell->getPort("\\B"));
- if (cell->hasPort("\\S"))
- S = assign_map(cell->getPort("\\S"));
+ if (cell->hasPort(ID::A))
+ A = assign_map(cell->getPort(ID::A));
+ if (cell->hasPort(ID::B))
+ B = assign_map(cell->getPort(ID::B));
+ if (cell->hasPort(ID::S))
+ S = assign_map(cell->getPort(ID::S));
A.replace(input_sig, RTLIL::SigSpec(in_val));
B.replace(input_sig, RTLIL::SigSpec(in_val));
S.replace(input_sig, RTLIL::SigSpec(in_val));
@@ -178,14 +178,14 @@ struct FsmExpand
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size();
- RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
new_ctrl_in.append(input_sig);
- fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
+ fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size();
- RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
new_ctrl_out.append(output_sig);
- fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
+ fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
@@ -246,7 +246,7 @@ struct FsmExpand
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
already_optimized = false;
- limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
for (create_current_set(); current_set.size() > 0; create_current_set()) {
for (auto c : current_set)
@@ -295,15 +295,13 @@ struct FsmExpandPass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
- continue;
+ for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_cells.push_back(cell_it.second);
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_cells.push_back(cell);
for (auto c : fsm_cells) {
- FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
+ FsmExpand fsm_expand(c, design, mod, full_mode);
fsm_expand.execute();
}
}
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 8eb1872f0..c02a54ea2 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -57,7 +57,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
std::string kiss_name;
size_t i;
- attr_it = cell->attributes.find("\\fsm_export");
+ attr_it = cell->attributes.find(ID::fsm_export);
if (!filename.empty()) {
kiss_name.assign(filename);
} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
@@ -173,16 +173,15 @@ struct FsmExportPass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
- attr_it = cell_it.second->attributes.find("\\fsm_export");
- if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
- write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc);
- filename.clear();
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm)) {
+ attr_it = cell->attributes.find(ID::fsm_export);
+ if (!flag_noauto || (attr_it != cell->attributes.end())) {
+ write_kiss2(mod, cell, filename, flag_origenc);
+ filename.clear();
}
+ }
}
} FsmExportPass;
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index a85c3bec0..3840aabc8 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -70,15 +70,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") {
+ if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
}
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
- RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_aa = sig;
sig_aa.replace(sig_y, sig_a);
@@ -272,17 +272,17 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
+ if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
- RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
- RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
- clk = cell->getPort("\\CLK");
- clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
- if (cell->type == "$adff") {
- arst = cell->getPort("\\ARST");
- arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
- reset_state = cell->parameters["\\ARST_VALUE"];
+ RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
+ RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
+ clk = cell->getPort(ID::CLK);
+ clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
+ if (cell->type == ID($adff)) {
+ arst = cell->getPort(ID::ARST);
+ arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
+ reset_state = cell->parameters[ID::ARST_VALUE];
}
sig_q.replace(dff_out, sig_d, &dff_in);
break;
@@ -320,14 +320,14 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b;
- if (cell->hasPort("\\B"))
- sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
- if (cellport.second == "\\A" && !sig_b.is_fully_const())
+ if (cell->hasPort(ID::B))
+ sig_b = assign_map(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
+ if (cellport.second == ID::A && !sig_b.is_fully_const())
continue;
- if (cellport.second == "\\B" && !sig_a.is_fully_const())
+ if (cellport.second == ID::B && !sig_a.is_fully_const())
continue;
log(" found ctrl output: %s\n", log_signal(sig_y));
ctrl_out.append(sig_y);
@@ -368,21 +368,21 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
- RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
- fsm_cell->setPort("\\CLK", clk);
- fsm_cell->setPort("\\ARST", arst);
- fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0;
- fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0;
- fsm_cell->setPort("\\CTRL_IN", ctrl_in);
- fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
- fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
+ RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm));
+ fsm_cell->setPort(ID::CLK, clk);
+ fsm_cell->setPort(ID::ARST, arst);
+ fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
+ fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
+ fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
+ fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
+ fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell);
// rename original state wire
module->wires_.erase(wire->name);
- wire->attributes.erase("\\fsm_encoding");
+ wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
module->wires_[wire->name] = wire;
@@ -422,18 +422,11 @@ struct FsmExtractPass : public Pass {
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);
- CellTypes ct;
- ct.setup_internals();
- ct.setup_internals_mem();
- ct.setup_stdcells();
- ct.setup_stdcells_mem();
+ CellTypes ct(design);
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- module = mod_it.second;
+ module = mod;
assign_map.set(module);
sig2driver.clear();
@@ -446,15 +439,15 @@ struct FsmExtractPass : public Pass {
assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
- if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort("\\Y") &&
- cell->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+ if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) &&
+ cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
- if (cell->type == "$pmux") {
- RTLIL::SigSpec sel_sig = assign_map(cell->getPort("\\S"));
+ if (cell->type == ID($pmux)) {
+ RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
if (bit1 != bit2)
@@ -463,10 +456,9 @@ struct FsmExtractPass : public Pass {
}
std::vector<RTLIL::Wire*> wire_list;
- for (auto &wire_it : module->wires_)
- if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
- if (design->selected(module, wire_it.second))
- wire_list.push_back(wire_it.second);
+ for (auto wire : module->selected_wires())
+ if (wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes[ID::fsm_encoding].decode_string() != "none")
+ wire_list.push_back(wire);
for (auto wire : wire_list)
extract_fsm(wire);
}
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
index 0548259ee..90250f9b7 100644
--- a/passes/fsm/fsm_info.cc
+++ b/passes/fsm/fsm_info.cc
@@ -46,16 +46,15 @@ struct FsmInfoPass : public Pass {
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
- log("\n");
- log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());
- FsmData fsm_data;
- fsm_data.copy_from_cell(cell_it.second);
- fsm_data.log_info(cell_it.second);
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm)) {
+ log("\n");
+ log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
+ FsmData fsm_data;
+ fsm_data.copy_from_cell(cell);
+ fsm_data.log_info(cell);
+ }
}
} FsmInfoPass;
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 80913fda8..1765df092 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -74,15 +74,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(eq_wire));
- RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
- eq_cell->setPort("\\A", eq_sig_a);
- eq_cell->setPort("\\B", eq_sig_b);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
+ eq_cell->setPort(ID::A, eq_sig_a);
+ eq_cell->setPort(ID::B, eq_sig_b);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(eq_sig_b.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
std::set<int> complete_in_state_cache = it.second;
@@ -102,12 +102,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(or_wire));
- RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
- or_cell->setPort("\\A", or_sig);
- or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
- or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
- or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
+ or_cell->setPort(ID::A, or_sig);
+ or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
+ or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
+ or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
}
@@ -118,15 +118,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
cases_vector.append(RTLIL::SigSpec(and_wire));
- RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
- and_cell->setPort("\\A", and_sig.extract(0, 1));
- and_cell->setPort("\\B", and_sig.extract(1, 1));
- and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
- and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
- and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
- and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
+ and_cell->setPort(ID::A, and_sig.extract(0, 1));
+ and_cell->setPort(ID::B, and_sig.extract(1, 1));
+ and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
+ and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
+ and_cell->parameters[ID::B_WIDTH] = RTLIL::Const(1);
+ and_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
break;
}
case 1:
@@ -141,12 +141,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
if (cases_vector.size() > 1) {
- RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
- or_cell->setPort("\\A", cases_vector);
- or_cell->setPort("\\Y", output);
- or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
- or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
+ or_cell->setPort(ID::A, cases_vector);
+ or_cell->setPort(ID::Y, output);
+ or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
+ or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} else if (cases_vector.size() == 1) {
module->connect(RTLIL::SigSig(output, cases_vector));
} else {
@@ -161,31 +161,31 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
- RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
- RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
+ RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
// create state register
- RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
+ RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
- if (fsm_cell->getPort("\\ARST").is_fully_const()) {
- state_dff->type = "$dff";
+ if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
+ state_dff->type = ID($dff);
} else {
- state_dff->type = "$adff";
- state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
- state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
- for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
+ state_dff->type = ID($adff);
+ state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
+ state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
+ for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
- state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
+ state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
}
- state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
- state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
- state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
- state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
- state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
+ state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
+ state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
+ state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
+ state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
+ state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
// decode state register
@@ -212,20 +212,20 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
encoding_is_onehot = false;
- RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
- eq_cell->setPort("\\A", sig_a);
- eq_cell->setPort("\\B", sig_b);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
+ eq_cell->setPort(ID::A, sig_a);
+ eq_cell->setPort(ID::B, sig_b);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(sig_b.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
}
if (encoding_is_onehot)
- state_wire->set_bool_attribute("\\onehot");
+ state_wire->set_bool_attribute(ID::onehot);
// generate next_state signal
@@ -285,13 +285,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
}
- RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
- mux_cell->setPort("\\A", sig_a);
- mux_cell->setPort("\\B", sig_b);
- mux_cell->setPort("\\S", sig_s);
- mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
- mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
+ RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
+ mux_cell->setPort(ID::A, sig_a);
+ mux_cell->setPort(ID::B, sig_b);
+ mux_cell->setPort(ID::S, sig_s);
+ mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
+ mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
+ mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
}
}
@@ -336,15 +336,13 @@ struct FsmMapPass : public Pass {
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
- continue;
+ for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_cells.push_back(cell_it.second);
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_cells.push_back(cell);
for (auto cell : fsm_cells)
- map_fsm(cell, mod_it.second);
+ map_fsm(cell, mod);
}
}
} FsmMapPass;
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 048daee55..89e8132d4 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -81,10 +81,10 @@ struct FsmOpt
{
RTLIL::SigBit bit = sig.as_bit();
- if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
+ if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0)
return false;
- char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
+ char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str());
for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
if (tok[0] && bit.offset == atoi(tok)) {
free(str);
@@ -98,7 +98,7 @@ struct FsmOpt
void opt_const_and_unused_inputs()
{
- RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table;
@@ -119,15 +119,15 @@ struct FsmOpt
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
if (!ctrl_in_used[i]) {
- log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
+ log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
for (auto &tr : new_transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_in);
tmp.remove(i, 1);
tr.ctrl_in = tmp.as_const();
}
- RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
new_ctrl_in.remove(i, 1);
- cell->setPort("\\CTRL_IN", new_ctrl_in);
+ cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_inputs--;
}
}
@@ -139,12 +139,12 @@ struct FsmOpt
void opt_unused_outputs()
{
for (int i = 0; i < fsm_data.num_outputs; i++) {
- RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
+ RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
if (signal_is_unused(sig)) {
log(" Removing unused output signal %s.\n", log_signal(sig));
- RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
new_ctrl_out.remove(i, 1);
- cell->setPort("\\CTRL_OUT", new_ctrl_out);
+ cell->setPort(ID::CTRL_OUT, new_ctrl_out);
for (auto &tr : fsm_data.transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_out);
tmp.remove(i, 1);
@@ -158,7 +158,7 @@ struct FsmOpt
void opt_alias_inputs()
{
- RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
+ RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
for (int i = 0; i < ctrl_in.size(); i++)
for (int j = i+1; j < ctrl_in.size(); j++)
@@ -195,8 +195,8 @@ struct FsmOpt
void opt_feedback_inputs()
{
- RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
- RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
+ RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
+ RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT];
for (int j = 0; j < ctrl_out.size(); j++)
for (int i = 0; i < ctrl_in.size(); i++)
@@ -340,12 +340,10 @@ struct FsmOptPass : public Pass {
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_) {
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- FsmData::optimize_fsm(cell_it.second, mod_it.second);
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ FsmData::optimize_fsm(cell, mod);
}
} FsmOptPass;
diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc
index fa1ff48cc..7edb923b9 100644
--- a/passes/fsm/fsm_recode.cc
+++ b/passes/fsm/fsm_recode.cc
@@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
{
- std::string name = cell->parameters["\\NAME"].decode_string();
+ std::string name = cell->parameters[ID::NAME].decode_string();
fprintf(f, "set_fsm_state_vector {");
for (int i = fsm_data.state_bits-1; i >= 0; i--)
@@ -53,7 +53,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding)
{
- std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
+ std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
@@ -95,7 +95,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
if (encfile)
- fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str());
+ fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
for (int i = 0; i < int(fsm_data.state_table.size()); i++)
@@ -181,11 +181,10 @@ struct FsmRecodePass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, encfile, default_encoding);
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
if (fm_set_fsm_file != NULL)
fclose(fm_set_fsm_file);
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 68222769a..47398b558 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -33,31 +33,31 @@ struct FsmData
void copy_to_cell(RTLIL::Cell *cell)
{
- cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs);
- cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs);
+ cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);
+ cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);
int state_num_log2 = 0;
for (int i = state_table.size(); i > 0; i = i >> 1)
state_num_log2++;
state_num_log2 = max(state_num_log2, 1);
- cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
- cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
- cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2);
- cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state);
- cell->parameters["\\STATE_TABLE"] = RTLIL::Const();
+ cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);
+ cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
+ cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
+ cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
+ cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
- std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits;
+ std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
- cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size());
- cell->parameters["\\TRANS_TABLE"] = RTLIL::Const();
+ cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
+ cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++)
{
- std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits;
+ std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
@@ -78,21 +78,21 @@ struct FsmData
void copy_from_cell(RTLIL::Cell *cell)
{
- num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int();
- num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int();
+ num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();
+ num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();
- state_bits = cell->parameters["\\STATE_BITS"].as_int();
- reset_state = cell->parameters["\\STATE_RST"].as_int();
+ state_bits = cell->parameters[ID::STATE_BITS].as_int();
+ reset_state = cell->parameters[ID::STATE_RST].as_int();
- int state_num = cell->parameters["\\STATE_NUM"].as_int();
- int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int();
- int trans_num = cell->parameters["\\TRANS_NUM"].as_int();
+ int state_num = cell->parameters[ID::STATE_NUM].as_int();
+ int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();
+ int trans_num = cell->parameters[ID::TRANS_NUM].as_int();
if (reset_state < 0 || reset_state >= state_num)
reset_state = -1;
- RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"];
- RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"];
+ RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
+ RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
@@ -134,7 +134,7 @@ struct FsmData
{
log("-------------------------------------\n");
log("\n");
- log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
+ log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
log("\n");
log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs);
@@ -142,13 +142,13 @@ struct FsmData
log("\n");
log(" Input signals:\n");
- RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
- RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 20:23:31 +0000