diff options
Diffstat (limited to 'passes/hierarchy/hierarchy.cc')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 04274990d..287f93097 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -50,17 +50,21 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell for (auto &celltype : found_celltypes) { std::set<std::string> portnames; + std::set<std::string> parameters; std::map<std::string, int> portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules) for (auto i2 : i1.second->cells) - if (i2.second->type == celltype) + if (i2.second->type == celltype) { for (auto &conn : i2.second->connections) { if (conn.first[0] != '$') portnames.insert(conn.first); portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width); } + for (auto ¶ : i2.second->parameters) + parameters.insert(para.first); + } for (auto &decl : portdecls) if (decl.index > 0) @@ -109,6 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; + mod->attributes["\\placeholder"] = RTLIL::Const(0, 0); design->modules[mod->name] = mod; for (auto &decl : ports) { @@ -121,6 +126,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell mod->add(wire); } + for (auto ¶ : parameters) + log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); + log(" module %s created.\n", RTLIL::id2cstr(mod->name)); } } @@ -139,9 +147,12 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla } if (cell->parameters.size() == 0) continue; + if (design->modules.at(cell->type)->attributes.count("\\placeholder") > 0) + continue; RTLIL::Module *mod = design->modules[cell->type]; cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); + did_something = true; } if (did_something) @@ -200,7 +211,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (auto_sizes.size() > 0) { module->update_auto_wires(auto_sizes); - log_header("Continuing EXPAND pass.\n"); + log_header("Continuing HIERARCHY pass.\n"); did_something = true; } @@ -262,7 +273,7 @@ struct HierarchyPass : public Pass { log(" use the specified top module to built a design hierarchy. modules\n"); log(" outside this tree (unused modules) are removed.\n"); log("\n"); - log("In -generate mode this pass generates skeletton modules for the given cell\n"); + log("In -generate mode this pass generates placeholder modules for the given cell\n"); log("types (wildcards supported). For this the design is searched for cells that\n"); log("match the given types and then the given port declarations are used to\n"); log("determine the direction of the ports. The syntax for a port declaration is:\n"); |