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-rw-r--r--passes/hierarchy/submod.cc131
1 files changed, 84 insertions, 47 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ec242aa1f..14974666e 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
+#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@@ -32,8 +33,11 @@ struct SubmodWorker
CellTypes ct;
RTLIL::Design *design;
RTLIL::Module *module;
+ SigMap sigmap;
+ pool<SigBit> outputs;
bool copy_mode;
+ bool hidden_mode;
std::string opt_name;
struct SubModule
@@ -44,44 +48,44 @@ struct SubmodWorker
std::map<std::string, SubModule> submodules;
- struct wire_flags_t {
+ struct bit_flags_t {
RTLIL::Wire *new_wire;
bool is_int_driven, is_int_used, is_ext_driven, is_ext_used;
- wire_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
+ bit_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
};
- std::map<RTLIL::Wire*, wire_flags_t> wire_flags;
+ std::map<SigBit, bit_flags_t> bit_flags;
bool flag_found_something;
- void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+ void flag_bit(RTLIL::SigBit bit, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
- if (wire_flags.count(wire) == 0) {
+ if (bit_flags.count(bit) == 0) {
if (!create)
return;
- wire_flags[wire] = wire_flags_t();
+ bit_flags[bit] = bit_flags_t();
}
if (set_int_driven)
- wire_flags[wire].is_int_driven = true;
+ bit_flags[bit].is_int_driven = true;
if (set_int_used)
- wire_flags[wire].is_int_used = true;
+ bit_flags[bit].is_int_used = true;
if (set_ext_driven)
- wire_flags[wire].is_ext_driven = true;
+ bit_flags[bit].is_ext_driven = true;
if (set_ext_used)
- wire_flags[wire].is_ext_used = true;
+ bit_flags[bit].is_ext_used = true;
flag_found_something = true;
}
void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
- for (auto &c : sig.chunks())
- if (c.wire != NULL)
- flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
+ for (auto &b : sig)
+ if (b.wire != NULL)
+ flag_bit(b, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
}
void handle_submodule(SubModule &submod)
{
log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
- wire_flags.clear();
+ bit_flags.clear();
for (RTLIL::Cell *cell : submod.cells) {
if (ct.cell_known(cell->type)) {
for (auto &conn : cell->connections())
@@ -114,18 +118,19 @@ struct SubmodWorker
int auto_name_counter = 1;
std::set<RTLIL::IdString> all_wire_names;
- for (auto &it : wire_flags) {
- all_wire_names.insert(it.first->name);
+ for (auto &it : bit_flags) {
+ all_wire_names.insert(it.first.wire->name);
}
- for (auto &it : wire_flags)
+ for (auto &it : bit_flags)
{
- RTLIL::Wire *wire = it.first;
- wire_flags_t &flags = it.second;
+ const RTLIL::SigBit &bit = it.first;
+ RTLIL::Wire *wire = bit.wire;
+ bit_flags_t &flags = it.second;
if (wire->port_input)
flags.is_ext_driven = true;
- if (wire->port_output)
+ if (outputs.count(bit))
flags.is_ext_used = true;
bool new_wire_port_input = false;
@@ -139,22 +144,36 @@ struct SubmodWorker
if (flags.is_int_driven && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
- std::string new_wire_name = wire->name.str();
+ RTLIL::IdString new_wire_name;
+ if (GetSize(wire) == 1)
+ new_wire_name = wire->name;
+ else
+ new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
if (new_wire_port_input || new_wire_port_output) {
- while (new_wire_name[0] == '$') {
- std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
- if (all_wire_names.count(next_wire_name) == 0) {
- all_wire_names.insert(next_wire_name);
- new_wire_name = next_wire_name;
+ if (new_wire_name[0] == '$')
+ while (1) {
+ std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++);
+ if (all_wire_names.count(next_wire_name) == 0) {
+ all_wire_names.insert(next_wire_name);
+ new_wire_name = next_wire_name;
+ break;
+ }
}
- }
+ else if (hidden_mode)
+ new_wire_name = stringf("$submod%s", new_wire_name.c_str());
}
- RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
+ RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);
new_wire->port_input = new_wire_port_input;
new_wire->port_output = new_wire_port_output;
- new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
+ if (new_wire->port_output) {
+ auto it = wire->attributes.find(ID(init));
+ if (it != wire->attributes.end()) {
+ new_wire->attributes[ID(init)] = it->second[bit.offset];
+ it->second[bit.offset] = State::Sx;
+ }
+ }
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
@@ -176,8 +195,8 @@ struct SubmodWorker
for (auto &conn : new_cell->connections_)
for (auto &bit : conn.second)
if (bit.wire != NULL) {
- log_assert(wire_flags.count(bit.wire) > 0);
- bit.wire = wire_flags[bit.wire].new_wire;
+ log_assert(bit_flags.count(bit) > 0);
+ bit = bit_flags[bit].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
if (!copy_mode)
@@ -187,18 +206,18 @@ struct SubmodWorker
if (!copy_mode) {
RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
- for (auto &it : wire_flags)
+ for (auto &it : bit_flags)
{
- RTLIL::Wire *old_wire = it.first;
+ RTLIL::SigBit old_bit = it.first;
RTLIL::Wire *new_wire = it.second.new_wire;
if (new_wire->port_id > 0)
- new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
+ new_cell->setPort(new_wire->name, old_bit);
}
}
}
- SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, std::string opt_name = std::string()) :
- design(design), module(module), copy_mode(copy_mode), opt_name(opt_name)
+ SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
+ design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
{
if (!design->selected_whole_module(module->name) && opt_name.empty())
return;
@@ -219,6 +238,15 @@ struct SubmodWorker
ct.setup_stdcells_mem();
ct.setup_design(design);
+ for (auto port : module->ports) {
+ auto wire = module->wire(port);
+ if (!wire->port_output)
+ continue;
+ for (auto b : sigmap(wire))
+ if (b.wire)
+ outputs.insert(b);
+ }
+
if (opt_name.empty())
{
for (auto &it : module->wires_)
@@ -273,7 +301,7 @@ struct SubmodPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" submod [-copy] [selection]\n");
+ log(" submod [options] [selection]\n");
log("\n");
log("This pass identifies all cells with the 'submod' attribute and moves them to\n");
log("a newly created module. The value of the attribute is used as name for the\n");
@@ -285,16 +313,20 @@ struct SubmodPass : public Pass {
log("This pass only operates on completely selected modules with no processes\n");
log("or memories.\n");
log("\n");
+ log(" -copy\n");
+ log(" by default the cells are 'moved' from the source module and the source\n");
+ log(" module will use an instance of the new module after this command is\n");
+ log(" finished. call with -copy to not modify the source module.\n");
log("\n");
- log(" submod -name <name> [-copy] [selection]\n");
- log("\n");
- log("As above, but don't use the 'submod' attribute but instead use the selection.\n");
- log("Only objects from one module might be selected. The value of the -name option\n");
- log("is used as the value of the 'submod' attribute above.\n");
+ log(" -name <name>\n");
+ log(" don't use the 'submod' attribute but instead use the selection. only\n");
+ log(" objects from one module might be selected. the value of the -name option\n");
+ log(" is used as the value of the 'submod' attribute instead.\n");
log("\n");
- log("By default the cells are 'moved' from the source module and the source module\n");
- log("will use an instance of the new module after this command is finished. Call\n");
- log("with -copy to not modify the source module.\n");
+ log(" -hidden\n");
+ log(" instead of creating submodule ports with public names, create ports with\n");
+ log(" private names so that a subsequent 'flatten; clean' call will restore the\n");
+ log(" original module with original public names.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -304,6 +336,7 @@ struct SubmodPass : public Pass {
std::string opt_name;
bool copy_mode = false;
+ bool hidden_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@@ -315,6 +348,10 @@ struct SubmodPass : public Pass {
copy_mode = true;
continue;
}
+ if (args[argidx] == "-hidden") {
+ hidden_mode = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -335,7 +372,7 @@ struct SubmodPass : public Pass {
queued_modules.push_back(mod_it.first);
for (auto &modname : queued_modules)
if (design->modules_.count(modname) != 0) {
- SubmodWorker worker(design, design->modules_[modname], copy_mode);
+ SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode);
handled_modules.insert(modname);
did_something = true;
}
@@ -358,7 +395,7 @@ struct SubmodPass : public Pass {
else {
Pass::call_on_module(design, module, "opt_clean");
log_header(design, "Continuing SUBMOD pass.\n");
- SubmodWorker worker(design, module, copy_mode, opt_name);
+ SubmodWorker worker(design, module, copy_mode, hidden_mode, opt_name);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 09:57:22 +0000