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-rw-r--r--passes/hierarchy/Makefile.inc1
-rw-r--r--passes/hierarchy/clkpart.cc269
-rw-r--r--passes/hierarchy/submod.cc74
3 files changed, 315 insertions, 29 deletions
diff --git a/passes/hierarchy/Makefile.inc b/passes/hierarchy/Makefile.inc
index b3f139b72..ea809ec08 100644
--- a/passes/hierarchy/Makefile.inc
+++ b/passes/hierarchy/Makefile.inc
@@ -2,4 +2,5 @@
OBJS += passes/hierarchy/hierarchy.o
OBJS += passes/hierarchy/uniquify.o
OBJS += passes/hierarchy/submod.o
+OBJS += passes/hierarchy/clkpart.o
diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc
new file mode 100644
index 000000000..8f671c175
--- /dev/null
+++ b/passes/hierarchy/clkpart.cc
@@ -0,0 +1,269 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ClkPartPass : public Pass {
+ ClkPartPass() : Pass("clkpart", "partition design according to clock domain") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" clkpart [options] [selection]\n");
+ log("\n");
+ log("Partition the contents of selected modules according to the clock (and optionally\n");
+ log("the enable) domains of its $_DFF* cells by extracting them into sub-modules,\n");
+ log("using the `submod` command.\n");
+ log("Sub-modules created by this command are marked with a 'clkpart' attribute.\n");
+ log("\n");
+ log(" -unpart\n");
+ log(" undo this operation within the selected modules, by flattening those with\n");
+ log(" a 'clkpart' attribute into those modules without this attribute.\n");
+ log("\n");
+ log(" -enable\n");
+ log(" also consider enable domains.\n");
+ log("\n");
+ }
+
+ bool unpart_mode, enable_mode;
+
+ void clear_flags() YS_OVERRIDE
+ {
+ unpart_mode = false;
+ enable_mode = false;
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing CLKPART pass (partition design according to clock domain).\n");
+ log_push();
+
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-unpart") {
+ unpart_mode = true;
+ continue;
+ }
+ if (args[argidx] == "-enable") {
+ enable_mode = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (unpart_mode)
+ unpart(design);
+ else
+ part(design);
+
+ log_pop();
+ }
+
+ void part(RTLIL::Design *design)
+ {
+ CellTypes ct(design);
+ SigMap assign_map;
+
+ for (auto mod : design->selected_modules())
+ {
+ if (mod->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(mod));
+ continue;
+ }
+
+ assign_map.set(mod);
+
+ std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
+ std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
+
+ std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
+ std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
+ std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
+
+ typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
+ std::map<clkdomain_t, vector<RTLIL::IdString>> assigned_cells;
+ std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
+
+ std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
+ std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
+
+ for (auto cell : all_cells)
+ {
+ clkdomain_t key;
+
+ for (auto &conn : cell->connections())
+ for (auto bit : conn.second) {
+ bit = assign_map(bit);
+ if (bit.wire != nullptr) {
+ cell_to_bit[cell].insert(bit);
+ bit_to_cell[bit].insert(cell);
+ if (ct.cell_input(cell->type, conn.first)) {
+ cell_to_bit_up[cell].insert(bit);
+ bit_to_cell_down[bit].insert(cell);
+ }
+ if (ct.cell_output(cell->type, conn.first)) {
+ cell_to_bit_down[cell].insert(bit);
+ bit_to_cell_up[bit].insert(cell);
+ }
+ }
+ }
+
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ {
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
+ }
+ else
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ {
+ bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
+ bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
+ }
+ else
+ continue;
+
+ unassigned_cells.erase(cell);
+ expand_queue.insert(cell);
+ expand_queue_up.insert(cell);
+ expand_queue_down.insert(cell);
+
+ assigned_cells[key].push_back(cell->name);
+ assigned_cells_reverse[cell] = key;
+ }
+
+ while (!expand_queue_up.empty() || !expand_queue_down.empty())
+ {
+ if (!expand_queue_up.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue_up.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue_up.erase(cell);
+
+ for (auto bit : cell_to_bit_up[cell])
+ for (auto c : bit_to_cell_up[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue_up.insert(c);
+ assigned_cells[key].push_back(c->name);
+ assigned_cells_reverse[c] = key;
+ expand_queue.insert(c);
+ }
+ }
+
+ if (!expand_queue_down.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue_down.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue_down.erase(cell);
+
+ for (auto bit : cell_to_bit_down[cell])
+ for (auto c : bit_to_cell_down[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue_up.insert(c);
+ assigned_cells[key].push_back(c->name);
+ assigned_cells_reverse[c] = key;
+ expand_queue.insert(c);
+ }
+ }
+
+ if (expand_queue_up.empty() && expand_queue_down.empty()) {
+ expand_queue_up.swap(next_expand_queue_up);
+ expand_queue_down.swap(next_expand_queue_down);
+ }
+ }
+
+ while (!expand_queue.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue.erase(cell);
+
+ for (auto bit : cell_to_bit.at(cell)) {
+ for (auto c : bit_to_cell[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue.insert(c);
+ assigned_cells[key].push_back(c->name);
+ assigned_cells_reverse[c] = key;
+ }
+ bit_to_cell[bit].clear();
+ }
+
+ if (expand_queue.empty())
+ expand_queue.swap(next_expand_queue);
+ }
+
+ clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
+ for (auto cell : unassigned_cells) {
+ assigned_cells[key].push_back(cell->name);
+ assigned_cells_reverse[cell] = key;
+ }
+
+ log_header(design, "Summary of detected clock domains:\n");
+ for (auto &it : assigned_cells)
+ log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
+ std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
+ std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
+
+ if (assigned_cells.size() > 1)
+ for (auto &it : assigned_cells) {
+ RTLIL::Selection sel(false);
+ sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
+
+ RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
+ Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
+
+ design->module(submod)->set_bool_attribute(ID(clkpart));
+ }
+ }
+ }
+
+ void unpart(RTLIL::Design *design)
+ {
+ vector<Module*> keeped;
+ for (auto mod : design->selected_modules()) {
+ if (mod->get_bool_attribute(ID(clkpart)))
+ continue;
+ if (mod->get_bool_attribute(ID(keep_hierarchy)))
+ continue;
+ keeped.push_back(mod);
+ mod->set_bool_attribute(ID(keep_hierarchy));
+ }
+
+ Pass::call(design, "flatten");
+
+ for (auto mod : keeped)
+ mod->set_bool_attribute(ID(keep_hierarchy), false);
+
+ }
+} ClkPartPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ec242aa1f..212932e46 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
+#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@@ -32,6 +33,8 @@ struct SubmodWorker
CellTypes ct;
RTLIL::Design *design;
RTLIL::Module *module;
+ SigMap sigmap;
+ pool<SigBit> outputs;
bool copy_mode;
std::string opt_name;
@@ -44,44 +47,44 @@ struct SubmodWorker
std::map<std::string, SubModule> submodules;
- struct wire_flags_t {
+ struct bit_flags_t {
RTLIL::Wire *new_wire;
bool is_int_driven, is_int_used, is_ext_driven, is_ext_used;
- wire_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
+ bit_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
};
- std::map<RTLIL::Wire*, wire_flags_t> wire_flags;
+ std::map<SigBit, bit_flags_t> bit_flags;
bool flag_found_something;
- void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+ void flag_bit(RTLIL::SigBit bit, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
- if (wire_flags.count(wire) == 0) {
+ if (bit_flags.count(bit) == 0) {
if (!create)
return;
- wire_flags[wire] = wire_flags_t();
+ bit_flags[bit] = bit_flags_t();
}
if (set_int_driven)
- wire_flags[wire].is_int_driven = true;
+ bit_flags[bit].is_int_driven = true;
if (set_int_used)
- wire_flags[wire].is_int_used = true;
+ bit_flags[bit].is_int_used = true;
if (set_ext_driven)
- wire_flags[wire].is_ext_driven = true;
+ bit_flags[bit].is_ext_driven = true;
if (set_ext_used)
- wire_flags[wire].is_ext_used = true;
+ bit_flags[bit].is_ext_used = true;
flag_found_something = true;
}
void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
- for (auto &c : sig.chunks())
- if (c.wire != NULL)
- flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
+ for (auto &b : sig)
+ if (b.wire != NULL)
+ flag_bit(b, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
}
void handle_submodule(SubModule &submod)
{
log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
- wire_flags.clear();
+ bit_flags.clear();
for (RTLIL::Cell *cell : submod.cells) {
if (ct.cell_known(cell->type)) {
for (auto &conn : cell->connections())
@@ -114,18 +117,19 @@ struct SubmodWorker
int auto_name_counter = 1;
std::set<RTLIL::IdString> all_wire_names;
- for (auto &it : wire_flags) {
- all_wire_names.insert(it.first->name);
+ for (auto &it : bit_flags) {
+ all_wire_names.insert(it.first.wire->name);
}
- for (auto &it : wire_flags)
+ for (auto &it : bit_flags)
{
- RTLIL::Wire *wire = it.first;
- wire_flags_t &flags = it.second;
+ const RTLIL::SigBit &bit = it.first;
+ RTLIL::Wire *wire = bit.wire;
+ bit_flags_t &flags = it.second;
if (wire->port_input)
flags.is_ext_driven = true;
- if (wire->port_output)
+ if (outputs.count(bit))
flags.is_ext_used = true;
bool new_wire_port_input = false;
@@ -139,7 +143,11 @@ struct SubmodWorker
if (flags.is_int_driven && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
- std::string new_wire_name = wire->name.str();
+ RTLIL::IdString new_wire_name;
+ if (GetSize(wire) == 1)
+ new_wire_name = wire->name;
+ else
+ new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
if (new_wire_port_input || new_wire_port_output) {
while (new_wire_name[0] == '$') {
std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
@@ -150,10 +158,9 @@ struct SubmodWorker
}
}
- RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
+ RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);
new_wire->port_input = new_wire_port_input;
new_wire->port_output = new_wire_port_output;
- new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
if (new_wire->port_input && new_wire->port_output)
@@ -176,8 +183,8 @@ struct SubmodWorker
for (auto &conn : new_cell->connections_)
for (auto &bit : conn.second)
if (bit.wire != NULL) {
- log_assert(wire_flags.count(bit.wire) > 0);
- bit.wire = wire_flags[bit.wire].new_wire;
+ log_assert(bit_flags.count(bit) > 0);
+ bit = bit_flags[bit].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
if (!copy_mode)
@@ -187,18 +194,18 @@ struct SubmodWorker
if (!copy_mode) {
RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
- for (auto &it : wire_flags)
+ for (auto &it : bit_flags)
{
- RTLIL::Wire *old_wire = it.first;
+ RTLIL::SigBit old_bit = it.first;
RTLIL::Wire *new_wire = it.second.new_wire;
if (new_wire->port_id > 0)
- new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
+ new_cell->setPort(new_wire->name, old_bit);
}
}
}
SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, std::string opt_name = std::string()) :
- design(design), module(module), copy_mode(copy_mode), opt_name(opt_name)
+ design(design), module(module), sigmap(module), copy_mode(copy_mode), opt_name(opt_name)
{
if (!design->selected_whole_module(module->name) && opt_name.empty())
return;
@@ -219,6 +226,15 @@ struct SubmodWorker
ct.setup_stdcells_mem();
ct.setup_design(design);
+ for (auto port : module->ports) {
+ auto wire = module->wire(port);
+ if (!wire->port_output)
+ continue;
+ for (auto b : sigmap(wire))
+ if (b.wire)
+ outputs.insert(b);
+ }
+
if (opt_name.empty())
{
for (auto &it : module->wires_)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 07:45:36 +0000