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-rw-r--r--passes/hierarchy/Makefile.inc1
-rw-r--r--passes/hierarchy/clkpart.cc308
-rw-r--r--passes/hierarchy/submod.cc133
3 files changed, 406 insertions, 36 deletions
diff --git a/passes/hierarchy/Makefile.inc b/passes/hierarchy/Makefile.inc
index b3f139b72..ea809ec08 100644
--- a/passes/hierarchy/Makefile.inc
+++ b/passes/hierarchy/Makefile.inc
@@ -2,4 +2,5 @@
OBJS += passes/hierarchy/hierarchy.o
OBJS += passes/hierarchy/uniquify.o
OBJS += passes/hierarchy/submod.o
+OBJS += passes/hierarchy/clkpart.o
diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc
new file mode 100644
index 000000000..81983e226
--- /dev/null
+++ b/passes/hierarchy/clkpart.cc
@@ -0,0 +1,308 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ClkPartPass : public Pass {
+ ClkPartPass() : Pass("clkpart", "partition design according to clock/enable domain") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" clkpart [options] [selection]\n");
+ log("\n");
+ log("Partition the contents of selected modules according to the clock (and optionally\n");
+ log("the enable) domains of its $_DFF* cells by extracting them into sub-modules,\n");
+ log("using the `submod` command.\n");
+ log("\n");
+ log(" -set_attr <name> <value>\n");
+ log(" set the specified attribute on all sub-modules created.\n");
+ log("\n");
+ log(" -unpart <name>\n");
+ log(" undo this operation within the selected modules, by flattening those\n");
+ log(" attached with an <name> attribute into those modules without this\n");
+ log(" attribute.\n");
+ log("\n");
+ log(" -enable\n");
+ log(" also consider enable domains.\n");
+ log("\n");
+ }
+
+ bool unpart_mode, enable_mode;
+ IdString attr_name;
+ Const attr_value;
+
+ void clear_flags() YS_OVERRIDE
+ {
+ unpart_mode = false;
+ enable_mode = false;
+ attr_name = IdString();
+ attr_value = Const();
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing CLKPART pass (partition design according to clock/enable domain).\n");
+ log_push();
+
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-set_attr" && argidx+2 < args.size()) {
+ attr_name = RTLIL::escape_id(args[++argidx]);
+ attr_value = args[argidx++];
+ continue;
+ }
+ if (args[argidx] == "-unpart" && argidx+1 < args.size()) {
+ unpart_mode = true;
+ attr_name = RTLIL::escape_id(args[++argidx]);
+ continue;
+ }
+ if (args[argidx] == "-enable") {
+ enable_mode = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (unpart_mode)
+ unpart(design);
+ else
+ part(design);
+
+ log_pop();
+ }
+
+ void part(RTLIL::Design *design)
+ {
+ CellTypes ct(design);
+ SigMap assign_map;
+ std::vector<std::string> new_submods;
+
+ log_header(design, "Summary of detected clock domains:\n");
+ for (auto mod : design->selected_modules())
+ {
+ if (mod->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(mod));
+ continue;
+ }
+
+ assign_map.set(mod);
+
+ std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
+ std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
+
+ std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
+ std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
+ std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
+
+ typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
+ std::map<clkdomain_t, vector<Cell*>> assigned_cells;
+ std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
+
+ std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
+ std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
+
+ for (auto cell : all_cells)
+ {
+ clkdomain_t key;
+
+ for (auto &conn : cell->connections())
+ for (auto bit : conn.second) {
+ bit = assign_map(bit);
+ if (bit.wire != nullptr) {
+ cell_to_bit[cell].insert(bit);
+ bit_to_cell[bit].insert(cell);
+ if (ct.cell_input(cell->type, conn.first)) {
+ cell_to_bit_up[cell].insert(bit);
+ bit_to_cell_down[bit].insert(cell);
+ }
+ if (ct.cell_output(cell->type, conn.first)) {
+ cell_to_bit_down[cell].insert(bit);
+ bit_to_cell_up[bit].insert(cell);
+ }
+ }
+ }
+
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ {
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
+ }
+ else
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ {
+ bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
+ bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
+ }
+ else
+ if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
+ {
+ bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_));
+ log_assert(!enable_mode); // TODO
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
+ }
+ else
+ continue;
+
+ unassigned_cells.erase(cell);
+ expand_queue.insert(cell);
+ expand_queue_up.insert(cell);
+ expand_queue_down.insert(cell);
+
+ assigned_cells[key].push_back(cell);
+ assigned_cells_reverse[cell] = key;
+ }
+
+ while (!expand_queue_up.empty() || !expand_queue_down.empty())
+ {
+ if (!expand_queue_up.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue_up.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue_up.erase(cell);
+
+ for (auto bit : cell_to_bit_up[cell])
+ for (auto c : bit_to_cell_up[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue_up.insert(c);
+ assigned_cells[key].push_back(c);
+ assigned_cells_reverse[c] = key;
+ expand_queue.insert(c);
+ }
+ }
+
+ if (!expand_queue_down.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue_down.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue_down.erase(cell);
+
+ for (auto bit : cell_to_bit_down[cell])
+ for (auto c : bit_to_cell_down[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue_up.insert(c);
+ assigned_cells[key].push_back(c);
+ assigned_cells_reverse[c] = key;
+ expand_queue.insert(c);
+ }
+ }
+
+ if (expand_queue_up.empty() && expand_queue_down.empty()) {
+ expand_queue_up.swap(next_expand_queue_up);
+ expand_queue_down.swap(next_expand_queue_down);
+ }
+ }
+
+ while (!expand_queue.empty())
+ {
+ RTLIL::Cell *cell = *expand_queue.begin();
+ clkdomain_t key = assigned_cells_reverse.at(cell);
+ expand_queue.erase(cell);
+
+ for (auto bit : cell_to_bit.at(cell)) {
+ for (auto c : bit_to_cell[bit])
+ if (unassigned_cells.count(c)) {
+ unassigned_cells.erase(c);
+ next_expand_queue.insert(c);
+ assigned_cells[key].push_back(c);
+ assigned_cells_reverse[c] = key;
+ }
+ bit_to_cell[bit].clear();
+ }
+
+ if (expand_queue.empty())
+ expand_queue.swap(next_expand_queue);
+ }
+
+ clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
+ for (auto cell : unassigned_cells) {
+ assigned_cells[key].push_back(cell);
+ assigned_cells_reverse[cell] = key;
+ }
+
+ clkdomain_t largest_domain;
+ int largest_domain_size = 0;
+ log(" module %s\n", mod->name.c_str());
+ for (auto &it : assigned_cells) {
+ log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
+ std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
+ std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
+ if (GetSize(it.second) > largest_domain_size) {
+ largest_domain = it.first;
+ largest_domain_size = GetSize(it.second);
+ }
+ }
+
+ for (auto &it : assigned_cells) {
+ if (it.first == largest_domain)
+ continue;
+
+ auto clk = std::get<1>(it.first);
+ auto en = std::get<3>(it.first);
+ std::string submod = stringf("clk=%s%s%s%s%s",
+ std::get<0>(it.first) ? "" : "!", clk.empty() ? "" : log_signal(clk),
+ std::get<2>(it.first) ? "" : "!", en.empty() ? "" : ".en=", en.empty() ? "" : log_signal(en));
+ for (auto c : it.second)
+ c->attributes[ID(submod)] = submod;
+ new_submods.push_back(stringf("%s_%s", mod->name.c_str(), submod.c_str()));
+ }
+ }
+
+ Pass::call(design, "submod -hidden");
+
+ if (!attr_name.empty())
+ for (auto m : new_submods)
+ design->module(m)->attributes[attr_name] = attr_value;
+ }
+
+ void unpart(RTLIL::Design *design)
+ {
+ vector<Module*> keeped;
+ for (auto mod : design->selected_modules()) {
+ if (mod->get_bool_attribute(attr_name))
+ continue;
+ if (mod->get_bool_attribute(ID(keep_hierarchy)))
+ continue;
+ keeped.push_back(mod);
+ mod->set_bool_attribute(ID(keep_hierarchy));
+ }
+
+ Pass::call(design, "flatten");
+
+ for (auto mod : keeped)
+ mod->set_bool_attribute(ID(keep_hierarchy), false);
+
+ }
+} ClkPartPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index ec242aa1f..cf27d2358 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -20,6 +20,7 @@
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
+#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <set>
@@ -32,8 +33,11 @@ struct SubmodWorker
CellTypes ct;
RTLIL::Design *design;
RTLIL::Module *module;
+ SigMap sigmap;
+ std::map<RTLIL::SigBit, RTLIL::SigBit> replace_const;
bool copy_mode;
+ bool hidden_mode;
std::string opt_name;
struct SubModule
@@ -46,35 +50,40 @@ struct SubmodWorker
struct wire_flags_t {
RTLIL::Wire *new_wire;
- bool is_int_driven, is_int_used, is_ext_driven, is_ext_used;
- wire_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
+ RTLIL::Const is_int_driven;
+ bool is_int_used, is_ext_driven, is_ext_used;
+ wire_flags_t(RTLIL::Wire* wire) : new_wire(NULL), is_int_driven(State::S0, GetSize(wire)), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
};
std::map<RTLIL::Wire*, wire_flags_t> wire_flags;
bool flag_found_something;
- void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+ void flag_wire(RTLIL::Wire *wire, bool create, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
if (wire_flags.count(wire) == 0) {
if (!create)
return;
- wire_flags[wire] = wire_flags_t();
+ wire_flags.emplace(wire, wire);
}
- if (set_int_driven)
- wire_flags[wire].is_int_driven = true;
if (set_int_used)
- wire_flags[wire].is_int_used = true;
+ wire_flags.at(wire).is_int_used = true;
if (set_ext_driven)
- wire_flags[wire].is_ext_driven = true;
+ wire_flags.at(wire).is_ext_driven = true;
if (set_ext_used)
- wire_flags[wire].is_ext_used = true;
+ wire_flags.at(wire).is_ext_used = true;
flag_found_something = true;
}
void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
for (auto &c : sig.chunks())
- if (c.wire != NULL)
- flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
+ if (c.wire != NULL) {
+ flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used);
+ if (set_int_driven)
+ for (int i = c.offset; i < c.offset+c.width; i++) {
+ wire_flags.at(c.wire).is_int_driven[i] = State::S1;
+ flag_found_something = true;
+ }
+ }
}
void handle_submodule(SubModule &submod)
@@ -127,27 +136,39 @@ struct SubmodWorker
flags.is_ext_driven = true;
if (wire->port_output)
flags.is_ext_used = true;
+ else {
+ auto sig = sigmap(wire);
+ for (auto c : sig.chunks())
+ if (c.wire && c.wire->port_output) {
+ flags.is_ext_used = true;
+ break;
+ }
+ }
bool new_wire_port_input = false;
bool new_wire_port_output = false;
- if (flags.is_int_driven && flags.is_ext_used)
+ if (!flags.is_int_driven.is_fully_zero() && flags.is_ext_used)
new_wire_port_output = true;
if (flags.is_ext_driven && flags.is_int_used)
new_wire_port_input = true;
- if (flags.is_int_driven && flags.is_ext_driven)
+ if (!flags.is_int_driven.is_fully_zero() && flags.is_ext_driven)
new_wire_port_input = true, new_wire_port_output = true;
std::string new_wire_name = wire->name.str();
if (new_wire_port_input || new_wire_port_output) {
- while (new_wire_name[0] == '$') {
- std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
- if (all_wire_names.count(next_wire_name) == 0) {
- all_wire_names.insert(next_wire_name);
- new_wire_name = next_wire_name;
+ if (new_wire_name[0] == '$')
+ while (1) {
+ std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++);
+ if (all_wire_names.count(next_wire_name) == 0) {
+ all_wire_names.insert(next_wire_name);
+ new_wire_name = next_wire_name;
+ break;
+ }
}
- }
+ else if (hidden_mode)
+ new_wire_name = stringf("$submod%s", new_wire_name.c_str());
}
RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width);
@@ -155,6 +176,22 @@ struct SubmodWorker
new_wire->port_output = new_wire_port_output;
new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
+ if (new_wire->port_output) {
+ new_wire->attributes.erase(ID(init));
+ auto sig = sigmap(wire);
+ for (int i = 0; i < GetSize(sig); i++) {
+ if (flags.is_int_driven[i] == State::S0)
+ continue;
+ if (!sig[i].wire)
+ continue;
+ auto it = sig[i].wire->attributes.find(ID(init));
+ if (it != sig[i].wire->attributes.end()) {
+ auto jt = new_wire->attributes.insert(std::make_pair(ID(init), Const(State::Sx, GetSize(sig)))).first;
+ jt->second[i] = it->second[sig[i].offset];
+ it->second[sig[i].offset] = State::Sx;
+ }
+ }
+ }
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
@@ -177,7 +214,7 @@ struct SubmodWorker
for (auto &bit : conn.second)
if (bit.wire != NULL) {
log_assert(wire_flags.count(bit.wire) > 0);
- bit.wire = wire_flags[bit.wire].new_wire;
+ bit.wire = wire_flags.at(bit.wire).new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
if (!copy_mode)
@@ -189,16 +226,20 @@ struct SubmodWorker
RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
for (auto &it : wire_flags)
{
- RTLIL::Wire *old_wire = it.first;
+ RTLIL::SigSpec old_sig = sigmap(it.first);
RTLIL::Wire *new_wire = it.second.new_wire;
- if (new_wire->port_id > 0)
- new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
+ if (new_wire->port_id > 0) {
+ // Prevents "ERROR: Mismatch in directionality ..." when flattening
+ if (new_wire->port_output)
+ old_sig.replace(replace_const);
+ new_cell->setPort(new_wire->name, old_sig);
+ }
}
}
}
- SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, std::string opt_name = std::string()) :
- design(design), module(module), copy_mode(copy_mode), opt_name(opt_name)
+ SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
+ design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
{
if (!design->selected_whole_module(module->name) && opt_name.empty())
return;
@@ -219,6 +260,17 @@ struct SubmodWorker
ct.setup_stdcells_mem();
ct.setup_design(design);
+ for (auto port : module->ports) {
+ auto wire = module->wire(port);
+ if (wire->port_output)
+ sigmap.add(wire);
+ }
+ auto wire = module->addWire(NEW_ID);
+ replace_const.emplace(State::S0, wire);
+ replace_const.emplace(State::S1, wire);
+ replace_const.emplace(State::Sx, wire);
+ replace_const.emplace(State::Sz, wire);
+
if (opt_name.empty())
{
for (auto &it : module->wires_)
@@ -273,7 +325,7 @@ struct SubmodPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" submod [-copy] [selection]\n");
+ log(" submod [options] [selection]\n");
log("\n");
log("This pass identifies all cells with the 'submod' attribute and moves them to\n");
log("a newly created module. The value of the attribute is used as name for the\n");
@@ -285,16 +337,20 @@ struct SubmodPass : public Pass {
log("This pass only operates on completely selected modules with no processes\n");
log("or memories.\n");
log("\n");
+ log(" -copy\n");
+ log(" by default the cells are 'moved' from the source module and the source\n");
+ log(" module will use an instance of the new module after this command is\n");
+ log(" finished. call with -copy to not modify the source module.\n");
log("\n");
- log(" submod -name <name> [-copy] [selection]\n");
- log("\n");
- log("As above, but don't use the 'submod' attribute but instead use the selection.\n");
- log("Only objects from one module might be selected. The value of the -name option\n");
- log("is used as the value of the 'submod' attribute above.\n");
+ log(" -name <name>\n");
+ log(" don't use the 'submod' attribute but instead use the selection. only\n");
+ log(" objects from one module might be selected. the value of the -name option\n");
+ log(" is used as the value of the 'submod' attribute instead.\n");
log("\n");
- log("By default the cells are 'moved' from the source module and the source module\n");
- log("will use an instance of the new module after this command is finished. Call\n");
- log("with -copy to not modify the source module.\n");
+ log(" -hidden\n");
+ log(" instead of creating submodule ports with public names, create ports with\n");
+ log(" private names so that a subsequent 'flatten; clean' call will restore the\n");
+ log(" original module with original public names.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -304,6 +360,7 @@ struct SubmodPass : public Pass {
std::string opt_name;
bool copy_mode = false;
+ bool hidden_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
@@ -315,6 +372,10 @@ struct SubmodPass : public Pass {
copy_mode = true;
continue;
}
+ if (args[argidx] == "-hidden") {
+ hidden_mode = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -335,7 +396,7 @@ struct SubmodPass : public Pass {
queued_modules.push_back(mod_it.first);
for (auto &modname : queued_modules)
if (design->modules_.count(modname) != 0) {
- SubmodWorker worker(design, design->modules_[modname], copy_mode);
+ SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode);
handled_modules.insert(modname);
did_something = true;
}
@@ -358,7 +419,7 @@ struct SubmodPass : public Pass {
else {
Pass::call_on_module(design, module, "opt_clean");
log_header(design, "Continuing SUBMOD pass.\n");
- SubmodWorker worker(design, module, copy_mode, opt_name);
+ SubmodWorker worker(design, module, copy_mode, hidden_mode, opt_name);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 01:18:48 +0000