1 files changed, 23 insertions, 16 deletions

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 91b5759eb..5c0acb3e5 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -57,13 +57,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 	SigSpec sig_rd_transparent;
 	SigSpec sig_rd_addr;
 	SigSpec sig_rd_data;
+	SigSpec sig_rd_en;
 
 	std::vector<Cell*> memcells;
 
 	for (auto &cell_it : module->cells_) {
 		Cell *cell = cell_it.second;
 		if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
-			addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int());
+			addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int());
 			memcells.push_back(cell);
 		}
 	}
@@ -139,22 +140,27 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 			SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]);
 			SigSpec addr = sigmap(cell->getPort("\\ADDR"));
 			SigSpec data = sigmap(cell->getPort("\\DATA"));
+			SigSpec en = sigmap(cell->getPort("\\EN"));
 
-			clk.extend_u0(1, false);
-			clk_enable.extend_u0(1, false);
-			clk_polarity.extend_u0(1, false);
-			transparent.extend_u0(1, false);
-			addr.extend_u0(addr_bits, false);
-			data.extend_u0(memory->width, false);
-
-			sig_rd_clk.append(clk);
-			sig_rd_clk_enable.append(clk_enable);
-			sig_rd_clk_polarity.append(clk_polarity);
-			sig_rd_transparent.append(transparent);
-			sig_rd_addr.append(addr);
-			sig_rd_data.append(data);
-
-			rd_ports++;
+			if (!en.is_fully_zero())
+			{
+				clk.extend_u0(1, false);
+				clk_enable.extend_u0(1, false);
+				clk_polarity.extend_u0(1, false);
+				transparent.extend_u0(1, false);
+				addr.extend_u0(addr_bits, false);
+				data.extend_u0(memory->width, false);
+
+				sig_rd_clk.append(clk);
+				sig_rd_clk_enable.append(clk_enable);
+				sig_rd_clk_polarity.append(clk_polarity);
+				sig_rd_transparent.append(transparent);
+				sig_rd_addr.append(addr);
+				sig_rd_data.append(data);
+				sig_rd_en.append(en);
+
+				rd_ports++;
+			}
 			continue;
 		}
 	}
@@ -203,6 +209,7 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 	mem->setPort("\\RD_CLK", sig_rd_clk);
 	mem->setPort("\\RD_ADDR", sig_rd_addr);
 	mem->setPort("\\RD_DATA", sig_rd_data);
+	mem->setPort("\\RD_EN", sig_rd_en);
 
 	for (auto c : memcells)
 		module->remove(c);