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-rw-r--r--passes/memory/memory_collect.cc28
-rw-r--r--passes/memory/memory_dff.cc38
-rw-r--r--passes/memory/memory_map.cc70
-rw-r--r--passes/memory/memory_share.cc106
-rw-r--r--passes/memory/memory_unpack.cc14
5 files changed, 128 insertions, 128 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index aecb7bd6c..8887d1952 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -75,12 +75,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
wr_ports++;
del_cells.push_back(cell);
- RTLIL::SigSpec clk = cell->get("\\CLK");
+ RTLIL::SigSpec clk = cell->getPort("\\CLK");
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
- RTLIL::SigSpec addr = cell->get("\\ADDR");
- RTLIL::SigSpec data = cell->get("\\DATA");
- RTLIL::SigSpec en = cell->get("\\EN");
+ RTLIL::SigSpec addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec data = cell->getPort("\\DATA");
+ RTLIL::SigSpec en = cell->getPort("\\EN");
clk.extend(1, false);
clk_enable.extend(1, false);
@@ -102,12 +102,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
rd_ports++;
del_cells.push_back(cell);
- RTLIL::SigSpec clk = cell->get("\\CLK");
+ RTLIL::SigSpec clk = cell->getPort("\\CLK");
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
- RTLIL::SigSpec addr = cell->get("\\ADDR");
- RTLIL::SigSpec data = cell->get("\\DATA");
+ RTLIL::SigSpec addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec data = cell->getPort("\\DATA");
clk.extend(1, false);
clk_enable.extend(1, false);
@@ -146,10 +146,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
- mem->set("\\WR_CLK", sig_wr_clk);
- mem->set("\\WR_ADDR", sig_wr_addr);
- mem->set("\\WR_DATA", sig_wr_data);
- mem->set("\\WR_EN", sig_wr_en);
+ mem->setPort("\\WR_CLK", sig_wr_clk);
+ mem->setPort("\\WR_ADDR", sig_wr_addr);
+ mem->setPort("\\WR_DATA", sig_wr_data);
+ mem->setPort("\\WR_EN", sig_wr_en);
log_assert(sig_rd_clk.size() == rd_ports);
log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
- mem->set("\\RD_CLK", sig_rd_clk);
- mem->set("\\RD_ADDR", sig_rd_addr);
- mem->set("\\RD_DATA", sig_rd_data);
+ mem->setPort("\\RD_CLK", sig_rd_clk);
+ mem->setPort("\\RD_ADDR", sig_rd_addr);
+ mem->setPort("\\RD_DATA", sig_rd_data);
for (auto c : del_cells)
module->remove(c);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 6cbce781f..e92d726cc 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -43,21 +43,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
continue;
if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
- if (cell->get("\\CLK") != clk)
+ if (cell->getPort("\\CLK") != clk)
continue;
if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
continue;
}
- RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
+ RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
normalize_sig(module, q_norm);
- RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
+ RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
if (d.size() != 1)
continue;
bit = d;
- clk = cell->get("\\CLK");
+ clk = cell->getPort("\\CLK");
clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
goto replaced_this_bit;
}
@@ -76,29 +76,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
bool clk_polarity = 0;
- RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
log("no (compatible) $dff for address input found.\n");
return;
}
- RTLIL::SigSpec sig_data = cell->get("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
log("no (compatible) $dff for data input found.\n");
return;
}
- RTLIL::SigSpec sig_en = cell->get("\\EN");
+ RTLIL::SigSpec sig_en = cell->getPort("\\EN");
if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
log("no (compatible) $dff for enable input found.\n");
return;
}
if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
- cell->set("\\CLK", clk);
- cell->set("\\ADDR", sig_addr);
- cell->set("\\DATA", sig_data);
- cell->set("\\EN", sig_en);
+ cell->setPort("\\CLK", clk);
+ cell->setPort("\\ADDR", sig_addr);
+ cell->setPort("\\DATA", sig_data);
+ cell->setPort("\\EN", sig_en);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
log("merged $dff to cell.\n");
@@ -119,9 +119,9 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
for (auto cell : module->cells())
if (cell->type == "$dff") {
- RTLIL::SigSpec new_q = cell->get("\\Q");
+ RTLIL::SigSpec new_q = cell->getPort("\\Q");
new_q.replace(sig, new_sig);
- cell->set("\\Q", new_q);
+ cell->setPort("\\Q", new_q);
}
}
@@ -132,13 +132,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
bool clk_polarity = 0;
RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_data = cell->get("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
{
disconnect_dff(module, sig_data);
- cell->set("\\CLK", clk_data);
- cell->set("\\DATA", sig_data);
+ cell->setPort("\\CLK", clk_data);
+ cell->setPort("\\DATA", sig_data);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -147,12 +147,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
{
- cell->set("\\CLK", clk_addr);
- cell->set("\\ADDR", sig_addr);
+ cell->setPort("\\CLK", clk_addr);
+ cell->setPort("\\ADDR", sig_addr);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 0000bd507..f1917b972 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -61,20 +61,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
}
// all write ports must share the same clock
- RTLIL::SigSpec clocks = cell->get("\\WR_CLK");
+ RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) {
- RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i);
continue;
}
if (clocks_en.bits[i] != RTLIL::State::S1) {
- RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
if (wr_addr.is_fully_const()) {
// FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en
@@ -119,15 +119,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
- c->set("\\CLK", clocks.extract(0, 1));
+ c->setPort("\\CLK", clocks.extract(0, 1));
} else {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
- c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
+ c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
}
RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
data_reg_in.push_back(RTLIL::SigSpec(w_in));
- c->set("\\D", data_reg_in.back());
+ c->setPort("\\D", data_reg_in.back());
std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
if (module->wires_.count(w_out_name) > 0)
@@ -137,7 +137,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
w_out->start_offset = mem_offset;
data_reg_out.push_back(RTLIL::SigSpec(w_out));
- c->set("\\Q", data_reg_out.back());
+ c->setPort("\\Q", data_reg_out.back());
}
}
@@ -147,10 +147,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
{
- RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
std::vector<RTLIL::SigSpec> rd_signals;
- rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width));
+ rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
{
@@ -159,13 +159,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
- c->set("\\D", rd_addr);
+ c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+ c->setPort("\\D", rd_addr);
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
- c->set("\\Q", RTLIL::SigSpec(w));
+ c->setPort("\\Q", RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w);
}
else
@@ -173,15 +173,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
- c->set("\\Q", rd_signals.back());
+ c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+ c->setPort("\\Q", rd_signals.back());
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w));
- c->set("\\D", rd_signals.back());
+ c->setPort("\\D", rd_signals.back());
}
}
@@ -193,15 +193,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- c->set("\\Y", rd_signals[k]);
- c->set("\\S", rd_addr.extract(mem_abits-j-1, 1));
+ c->setPort("\\Y", rd_signals[k]);
+ c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1));
count_mux++;
- c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
- c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
+ c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
+ c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
- next_rd_signals.push_back(c->get("\\A"));
- next_rd_signals.push_back(c->get("\\B"));
+ next_rd_signals.push_back(c->getPort("\\A"));
+ next_rd_signals.push_back(c->getPort("\\B"));
}
next_rd_signals.swap(rd_signals);
@@ -222,9 +222,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
{
- RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width);
- RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
@@ -232,12 +232,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- c->set("\\A", RTLIL::SigSpec(i, mem_abits));
- c->set("\\B", wr_addr);
+ c->setPort("\\A", RTLIL::SigSpec(i, mem_abits));
+ c->setPort("\\B", wr_addr);
count_wrmux++;
RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y"));
- c->set("\\Y", w_seladdr);
+ c->setPort("\\Y", w_seladdr);
int wr_offset = 0;
while (wr_offset < wr_en.size())
@@ -262,21 +262,21 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- c->set("\\A", w);
- c->set("\\B", wr_bit);
+ c->setPort("\\A", w);
+ c->setPort("\\B", wr_bit);
w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
- c->set("\\Y", RTLIL::SigSpec(w));
+ c->setPort("\\Y", RTLIL::SigSpec(w));
}
c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
c->parameters["\\WIDTH"] = wr_width;
- c->set("\\A", sig.extract(wr_offset, wr_width));
- c->set("\\B", wr_data.extract(wr_offset, wr_width));
- c->set("\\S", RTLIL::SigSpec(w));
+ c->setPort("\\A", sig.extract(wr_offset, wr_width));
+ c->setPort("\\B", wr_data.extract(wr_offset, wr_width));
+ c->setPort("\\S", RTLIL::SigSpec(w));
w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
- c->set("\\Y", w);
+ c->setPort("\\Y", w);
sig.replace(wr_offset, w);
wr_offset += wr_width;
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index b1629b7c4..b6e7cc835 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -64,18 +64,18 @@ struct MemoryShareWorker
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
int bit_idx = sig_to_mux.at(sig).second;
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
log_assert(sig_y.at(bit_idx) == sig);
for (int i = 0; i < int(sig_s.size()); i++)
if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
- RTLIL::SigSpec new_b = cell->get("\\B");
+ RTLIL::SigSpec new_b = cell->getPort("\\B");
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->set("\\B", new_b);
+ cell->setPort("\\B", new_b);
}
return false;
}
@@ -90,9 +90,9 @@ struct MemoryShareWorker
new_state[sig_s[i]] = true;
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
- RTLIL::SigSpec new_b = cell->get("\\B");
+ RTLIL::SigSpec new_b = cell->getPort("\\B");
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->set("\\B", new_b);
+ cell->setPort("\\B", new_b);
}
}
@@ -101,9 +101,9 @@ struct MemoryShareWorker
new_state[sig_s[i]] = false;
if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
- RTLIL::SigSpec new_a = cell->get("\\A");
+ RTLIL::SigSpec new_a = cell->getPort("\\A");
new_a.replace(bit_idx, RTLIL::State::Sx);
- cell->set("\\A", new_a);
+ cell->setPort("\\A", new_a);
}
return false;
@@ -150,10 +150,10 @@ struct MemoryShareWorker
if (cell->type == "$mux" || cell->type == "$pmux")
{
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
non_feedback_nets.insert(sig_s.begin(), sig_s.end());
@@ -200,8 +200,8 @@ struct MemoryShareWorker
if (cell->parameters.at("\\CLK_ENABLE").as_bool())
continue;
- RTLIL::SigSpec sig_addr = sigmap(cell->get("\\ADDR"));
- std::vector<RTLIL::SigBit> sig_data = sigmap(cell->get("\\DATA"));
+ RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR"));
+ std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA"));
for (int i = 0; i < int(sig_data.size()); i++)
if (non_feedback_nets.count(sig_data[i]))
@@ -221,14 +221,14 @@ struct MemoryShareWorker
for (auto cell : wr_ports)
{
- RTLIL::SigSpec sig_addr = sigmap_xmux(cell->get("\\ADDR"));
+ RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR"));
if (!async_rd_bits.count(sig_addr))
continue;
log(" Analyzing write port %s.\n", log_id(cell));
- std::vector<RTLIL::SigBit> cell_data = cell->get("\\DATA");
- std::vector<RTLIL::SigBit> cell_en = cell->get("\\EN");
+ std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA");
+ std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN");
int created_conditions = 0;
for (int i = 0; i < int(cell_data.size()); i++)
@@ -248,7 +248,7 @@ struct MemoryShareWorker
if (created_conditions) {
log(" Added enable logic for %d different cases.\n", created_conditions);
- cell->set("\\EN", cell_en);
+ cell->setPort("\\EN", cell_en);
}
}
}
@@ -366,15 +366,15 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++)
{
RTLIL::Cell *cell = wr_ports.at(i);
- RTLIL::SigSpec addr = sigmap_xmux(cell->get("\\ADDR"));
+ RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR"));
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
+ (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
{
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->get("\\CLK"));
+ cache_clk = sigmap(cell->getPort("\\CLK"));
last_port_by_addr.clear();
if (cache_clk_enable)
@@ -386,7 +386,7 @@ struct MemoryShareWorker
log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--) {
active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
@@ -408,13 +408,13 @@ struct MemoryShareWorker
// Force this ports addr input to addr directly (skip don't care muxes)
- cell->set("\\ADDR", addr);
+ cell->setPort("\\ADDR", addr);
// If any of the ports between `last_i' and `i' write to the same address, this
// will have priority over whatever `last_i` wrote. So we need to revisit those
// ports and mask the EN bits accordingly.
- RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->get("\\EN"));
+ RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN"));
for (int j = last_i+1; j < i; j++)
{
@@ -429,20 +429,20 @@ struct MemoryShareWorker
found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j);
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
- module->addEq(NEW_ID, addr, wr_ports[j]->get("\\ADDR"), is_same_addr);
- merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->get("\\EN")));
+ module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr);
+ merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN")));
}
}
// Then we need to merge the (masked) EN and the DATA signals.
- RTLIL::SigSpec merged_data = wr_ports[last_i]->get("\\DATA");
+ RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA");
if (found_overlapping_bits) {
log(" Creating logic for merging DATA and EN ports.\n");
- merge_en_data(merged_en, merged_data, sigmap(cell->get("\\EN")), sigmap(cell->get("\\DATA")));
+ merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA")));
} else {
- RTLIL::SigSpec cell_en = sigmap(cell->get("\\EN"));
- RTLIL::SigSpec cell_data = sigmap(cell->get("\\DATA"));
+ RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN"));
+ RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA"));
for (int k = 0; k < int(en_bits.size()); k++)
if (!active_bits_on_port[last_i][k]) {
merged_en.replace(k, cell_en.extract(k, 1));
@@ -452,14 +452,14 @@ struct MemoryShareWorker
// Connect the new EN and DATA signals and remove the old write port.
- cell->set("\\EN", merged_en);
- cell->set("\\DATA", merged_data);
+ cell->setPort("\\EN", merged_en);
+ cell->setPort("\\DATA", merged_data);
module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL;
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--)
log("%c", active_bits_on_port[i][k] ? '1' : '0');
@@ -498,7 +498,7 @@ struct MemoryShareWorker
std::set<int> considered_port_pairs;
for (int i = 0; i < int(wr_ports.size()); i++) {
- std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+ std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
for (auto bit : bits)
if (bit == RTLIL::State::S1)
goto port_is_always_active;
@@ -518,12 +518,12 @@ struct MemoryShareWorker
RTLIL::Cell *cell = wr_ports.at(i);
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
+ (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
{
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->get("\\CLK"));
+ cache_clk = sigmap(cell->getPort("\\CLK"));
}
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
considered_port_pairs.insert(i);
@@ -551,7 +551,7 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++)
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
{
- RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+ RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
std::vector<RTLIL::SigBit> bits = sig;
@@ -594,18 +594,18 @@ struct MemoryShareWorker
log(" Merging port %d into port %d.\n", i-1, i);
port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
- RTLIL::SigSpec last_addr = wr_ports[i-1]->get("\\ADDR");
- RTLIL::SigSpec last_data = wr_ports[i-1]->get("\\DATA");
- std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->get("\\EN"));
+ RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR");
+ RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA");
+ std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN"));
- RTLIL::SigSpec this_addr = wr_ports[i]->get("\\ADDR");
- RTLIL::SigSpec this_data = wr_ports[i]->get("\\DATA");
- std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+ RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR");
+ RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA");
+ std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
- wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
- wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
+ wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
+ wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@@ -623,7 +623,7 @@ struct MemoryShareWorker
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
- wr_ports[i]->set("\\EN", en);
+ wr_ports[i]->setPort("\\EN", en);
module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL;
@@ -662,18 +662,18 @@ struct MemoryShareWorker
if (cell->type == "$mux")
{
- RTLIL::SigSpec sig_a = sigmap_xmux(cell->get("\\A"));
- RTLIL::SigSpec sig_b = sigmap_xmux(cell->get("\\B"));
+ RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B"));
if (sig_a.is_fully_undef())
- sigmap_xmux.add(cell->get("\\Y"), sig_b);
+ sigmap_xmux.add(cell->getPort("\\Y"), sig_b);
else if (sig_b.is_fully_undef())
- sigmap_xmux.add(cell->get("\\Y"), sig_a);
+ sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
}
if (cell->type == "$mux" || cell->type == "$pmux")
{
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < int(sig_y.size()); i++)
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
}
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 3f675edea..68e9a9697 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -53,9 +53,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
- cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1));
- cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits));
- cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width));
+ cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
+ cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
+ cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
}
for (int i = 0; i < num_wr_ports; i++)
@@ -67,10 +67,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\PRIORITY"] = i;
- cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1));
- cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width));
- cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits));
- cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width));
+ cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
+ cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
+ cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
+ cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
}
module->remove(memory);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 05:16:32 +0000