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-rw-r--r--passes/memory/memory_bram.cc64
-rw-r--r--passes/memory/memory_collect.cc92
-rw-r--r--passes/memory/memory_dff.cc106
-rw-r--r--passes/memory/memory_map.cc142
-rw-r--r--passes/memory/memory_memx.cc20
-rw-r--r--passes/memory/memory_nordff.cc40
-rw-r--r--passes/memory/memory_share.cc176
-rw-r--r--passes/memory/memory_unpack.cc82
8 files changed, 361 insertions, 361 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 24478f2ee..52ee1e99d 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -105,11 +105,11 @@ struct rules_t
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant);
if (abits != other.abits)
- variant_params["\\CFG_ABITS"] = abits;
+ variant_params[ID::CFG_ABITS] = abits;
if (dbits != other.dbits)
- variant_params["\\CFG_DBITS"] = dbits;
+ variant_params[ID::CFG_DBITS] = dbits;
if (init != other.init)
- variant_params["\\CFG_INIT"] = init;
+ variant_params[ID::CFG_INIT] = init;
for (int i = 0; i < groups; i++)
{
@@ -414,44 +414,44 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
// bram.dump_config();
- int mem_size = cell->getParam("\\SIZE").as_int();
- int mem_abits = cell->getParam("\\ABITS").as_int();
- int mem_width = cell->getParam("\\WIDTH").as_int();
- // int mem_offset = cell->getParam("\\OFFSET").as_int();
+ int mem_size = cell->getParam(ID::SIZE).as_int();
+ int mem_abits = cell->getParam(ID::ABITS).as_int();
+ int mem_width = cell->getParam(ID::WIDTH).as_int();
+ // int mem_offset = cell->getParam(ID::OFFSET).as_int();
- bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+ bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
vector<Const> initdata;
if (cell_init) {
- Const initparam = cell->getParam("\\INIT");
+ Const initparam = cell->getParam(ID::INIT);
initdata.reserve(mem_size);
for (int i=0; i < mem_size; i++)
initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx));
}
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
- auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE"));
- auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY"));
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
+ auto wr_clken = SigSpec(cell->getParam(ID::WR_CLK_ENABLE));
+ auto wr_clkpol = SigSpec(cell->getParam(ID::WR_CLK_POLARITY));
wr_clken.extend_u0(wr_ports);
wr_clkpol.extend_u0(wr_ports);
- SigSpec wr_en = cell->getPort("\\WR_EN");
- SigSpec wr_clk = cell->getPort("\\WR_CLK");
- SigSpec wr_data = cell->getPort("\\WR_DATA");
- SigSpec wr_addr = cell->getPort("\\WR_ADDR");
+ SigSpec wr_en = cell->getPort(ID::WR_EN);
+ SigSpec wr_clk = cell->getPort(ID::WR_CLK);
+ SigSpec wr_data = cell->getPort(ID::WR_DATA);
+ SigSpec wr_addr = cell->getPort(ID::WR_ADDR);
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- auto rd_clken = SigSpec(cell->getParam("\\RD_CLK_ENABLE"));
- auto rd_clkpol = SigSpec(cell->getParam("\\RD_CLK_POLARITY"));
- auto rd_transp = SigSpec(cell->getParam("\\RD_TRANSPARENT"));
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ auto rd_clken = SigSpec(cell->getParam(ID::RD_CLK_ENABLE));
+ auto rd_clkpol = SigSpec(cell->getParam(ID::RD_CLK_POLARITY));
+ auto rd_transp = SigSpec(cell->getParam(ID::RD_TRANSPARENT));
rd_clken.extend_u0(rd_ports);
rd_clkpol.extend_u0(rd_ports);
rd_transp.extend_u0(rd_ports);
- SigSpec rd_en = cell->getPort("\\RD_EN");
- SigSpec rd_clk = cell->getPort("\\RD_CLK");
- SigSpec rd_data = cell->getPort("\\RD_DATA");
- SigSpec rd_addr = cell->getPort("\\RD_ADDR");
+ SigSpec rd_en = cell->getPort(ID::RD_EN);
+ SigSpec rd_clk = cell->getPort(ID::RD_CLK);
+ SigSpec rd_data = cell->getPort(ID::RD_DATA);
+ SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
{
@@ -915,7 +915,7 @@ grow_read_ports:;
else
initparam[i*bram.dbits+j] = padding;
}
- c->setParam("\\INIT", initparam);
+ c->setParam(ID::INIT, initparam);
}
for (auto &pi : portinfos)
@@ -1048,14 +1048,14 @@ void handle_cell(Cell *cell, const rules_t &rules)
{
log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
- bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+ bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
dict<string, int> match_properties;
- match_properties["words"] = cell->getParam("\\SIZE").as_int();
- match_properties["abits"] = cell->getParam("\\ABITS").as_int();
- match_properties["dbits"] = cell->getParam("\\WIDTH").as_int();
- match_properties["wports"] = cell->getParam("\\WR_PORTS").as_int();
- match_properties["rports"] = cell->getParam("\\RD_PORTS").as_int();
+ match_properties["words"] = cell->getParam(ID::SIZE).as_int();
+ match_properties["abits"] = cell->getParam(ID::ABITS).as_int();
+ match_properties["dbits"] = cell->getParam(ID::WIDTH).as_int();
+ match_properties["wports"] = cell->getParam(ID::WR_PORTS).as_int();
+ match_properties["rports"] = cell->getParam(ID::RD_PORTS).as_int();
match_properties["bits"] = match_properties["words"] * match_properties["dbits"];
match_properties["ports"] = match_properties["wports"] + match_properties["rports"];
@@ -1357,7 +1357,7 @@ struct MemoryBramPass : public Pass {
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
handle_cell(cell, rules);
}
} MemoryBramPass;
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 9dcb3f024..a62dcc2c4 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -25,11 +25,11 @@ PRIVATE_NAMESPACE_BEGIN
bool memcells_cmp(Cell *a, Cell *b)
{
- if (a->type == "$memrd" && b->type == "$memrd")
+ if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name;
- if (a->type == "$memrd" || b->type == "$memrd")
- return (a->type == "$memrd") < (b->type == "$memrd");
- return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
+ if (a->type == ID($memrd) || b->type == ID($memrd))
+ return (a->type == ID($memrd)) < (b->type == ID($memrd));
+ return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
}
Cell *handle_memory(Module *module, RTLIL::Memory *memory)
@@ -62,8 +62,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
for (auto &cell_it : module->cells_) {
Cell *cell = cell_it.second;
- if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
+ if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) {
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
for (int i = 0; i < GetSize(addr); i++)
if (addr[i] != State::S0)
addr_bits = std::max(addr_bits, i+1);
@@ -90,10 +90,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
{
log(" %s (%s)\n", log_id(cell), log_id(cell->type));
- if (cell->type == "$meminit")
+ if (cell->type == ID($meminit))
{
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
@@ -112,14 +112,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
continue;
}
- if (cell->type == "$memwr")
+ if (cell->type == ID($memwr))
{
- SigSpec clk = sigmap(cell->getPort("\\CLK"));
- SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
- SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
- SigSpec en = sigmap(cell->getPort("\\EN"));
+ SigSpec clk = sigmap(cell->getPort(ID::CLK));
+ SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
+ SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
+ SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero())
{
@@ -142,15 +142,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
continue;
}
- if (cell->type == "$memrd")
+ if (cell->type == ID($memrd))
{
- SigSpec clk = sigmap(cell->getPort("\\CLK"));
- SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
- SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
- SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]);
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
- SigSpec en = sigmap(cell->getPort("\\EN"));
+ SigSpec clk = sigmap(cell->getPort(ID::CLK));
+ SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
+ SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
+ SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]);
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
+ SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero())
{
@@ -178,13 +178,13 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
std::stringstream sstr;
sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
- Cell *mem = module->addCell(sstr.str(), "$mem");
- mem->parameters["\\MEMID"] = Const(memory->name.str());
- mem->parameters["\\WIDTH"] = Const(memory->width);
- mem->parameters["\\OFFSET"] = Const(memory->start_offset);
- mem->parameters["\\SIZE"] = Const(memory->size);
- mem->parameters["\\ABITS"] = Const(addr_bits);
- mem->parameters["\\INIT"] = init_data;
+ Cell *mem = module->addCell(sstr.str(), ID($mem));
+ mem->parameters[ID::MEMID] = Const(memory->name.str());
+ mem->parameters[ID::WIDTH] = Const(memory->width);
+ mem->parameters[ID::OFFSET] = Const(memory->start_offset);
+ mem->parameters[ID::SIZE] = Const(memory->size);
+ mem->parameters[ID::ABITS] = Const(addr_bits);
+ mem->parameters[ID::INIT] = init_data;
log_assert(sig_wr_clk.size() == wr_ports);
log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
@@ -193,14 +193,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
log_assert(sig_wr_data.size() == wr_ports * memory->width);
log_assert(sig_wr_en.size() == wr_ports * memory->width);
- mem->parameters["\\WR_PORTS"] = Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
+ mem->parameters[ID::WR_PORTS] = Const(wr_ports);
+ mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
+ mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
- mem->setPort("\\WR_CLK", sig_wr_clk);
- mem->setPort("\\WR_ADDR", sig_wr_addr);
- mem->setPort("\\WR_DATA", sig_wr_data);
- mem->setPort("\\WR_EN", sig_wr_en);
+ mem->setPort(ID::WR_CLK, sig_wr_clk);
+ mem->setPort(ID::WR_ADDR, sig_wr_addr);
+ mem->setPort(ID::WR_DATA, sig_wr_data);
+ mem->setPort(ID::WR_EN, sig_wr_en);
log_assert(sig_rd_clk.size() == rd_ports);
log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@@ -208,15 +208,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
log_assert(sig_rd_data.size() == rd_ports * memory->width);
- mem->parameters["\\RD_PORTS"] = Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
+ mem->parameters[ID::RD_PORTS] = Const(rd_ports);
+ mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
+ mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
+ mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
- mem->setPort("\\RD_CLK", sig_rd_clk);
- mem->setPort("\\RD_ADDR", sig_rd_addr);
- mem->setPort("\\RD_DATA", sig_rd_data);
- mem->setPort("\\RD_EN", sig_rd_en);
+ mem->setPort(ID::RD_CLK, sig_rd_clk);
+ mem->setPort(ID::RD_ADDR, sig_rd_addr);
+ mem->setPort(ID::RD_DATA, sig_rd_data);
+ mem->setPort(ID::RD_EN, sig_rd_en);
// Copy attributes from RTLIL memory to $mem
for (auto attr : memory->attributes)
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index be4b3c100..726a5c1ff 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -39,10 +39,10 @@ struct MemoryDffWorker
MemoryDffWorker(Module *module) : module(module), sigmap(module)
{
for (auto wire : module->wires()) {
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec sig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sig[i]);
@@ -66,8 +66,8 @@ struct MemoryDffWorker
if (after && forward_merged_dffs.count(cell))
continue;
- SigSpec this_clk = cell->getPort("\\CLK");
- bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
+ SigSpec this_clk = cell->getPort(ID::CLK);
+ bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (invbits.count(this_clk)) {
this_clk = invbits.at(this_clk);
@@ -81,10 +81,10 @@ struct MemoryDffWorker
continue;
}
- RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
+ RTLIL::SigSpec q_norm = cell->getPort(after ? ID::D : ID::Q);
sigmap.apply(q_norm);
- RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
+ RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? ID::Q : ID::D));
if (d.size() != 1)
continue;
@@ -113,19 +113,19 @@ struct MemoryDffWorker
bool clk_polarity = 0;
candidate_dffs.clear();
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
log("no (compatible) $dff for address input found.\n");
return;
}
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
log("no (compatible) $dff for data input found.\n");
return;
}
- RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
log("no (compatible) $dff for enable input found.\n");
return;
@@ -136,12 +136,12 @@ struct MemoryDffWorker
for (auto cell : candidate_dffs)
forward_merged_dffs.insert(cell);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\ADDR", sig_addr);
- cell->setPort("\\DATA", sig_data);
- cell->setPort("\\EN", sig_en);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::ADDR, sig_addr);
+ cell->setPort(ID::DATA, sig_data);
+ cell->setPort(ID::EN, sig_en);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
log("merged $dff to cell.\n");
return;
@@ -161,10 +161,10 @@ struct MemoryDffWorker
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto cell : module->cells())
- if (cell->type == "$dff") {
- RTLIL::SigSpec new_q = cell->getPort("\\Q");
+ if (cell->type == ID($dff)) {
+ RTLIL::SigSpec new_q = cell->getPort(ID::Q);
new_q.replace(sig, new_sig);
- cell->setPort("\\Q", new_q);
+ cell->setPort(ID::Q, new_q);
}
}
@@ -175,7 +175,7 @@ struct MemoryDffWorker
bool clk_polarity = 0;
RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
for (auto bit : sigmap(sig_data))
if (sigbit_users_count[bit] > 1)
@@ -189,9 +189,9 @@ struct MemoryDffWorker
do {
bool enable_invert = mux_cells_a.count(sig_data) != 0;
Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
- check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
- sig_data = sigmap(mux->getPort("\\Y"));
- en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
+ check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A)));
+ sig_data = sigmap(mux->getPort(ID::Y));
+ en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S));
} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
for (auto bit : sig_data)
@@ -202,12 +202,12 @@ struct MemoryDffWorker
std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
{
disconnect_dff(sig_data);
- cell->setPort("\\CLK", clk_data);
- cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
- cell->setPort("\\DATA", sig_data);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, clk_data);
+ cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
+ cell->setPort(ID::DATA, sig_data);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff with rd enable to cell.\n");
return;
}
@@ -217,12 +217,12 @@ struct MemoryDffWorker
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
{
disconnect_dff(sig_data);
- cell->setPort("\\CLK", clk_data);
- cell->setPort("\\EN", State::S1);
- cell->setPort("\\DATA", sig_data);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, clk_data);
+ cell->setPort(ID::EN, State::S1);
+ cell->setPort(ID::DATA, sig_data);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff to cell.\n");
return;
}
@@ -230,16 +230,16 @@ struct MemoryDffWorker
skip_ff_after_read_merging:;
RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
{
- cell->setPort("\\CLK", clk_addr);
- cell->setPort("\\EN", State::S1);
- cell->setPort("\\ADDR", sig_addr);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
+ cell->setPort(ID::CLK, clk_addr);
+ cell->setPort(ID::EN, State::S1);
+ cell->setPort(ID::ADDR, sig_addr);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(1);
log("merged address $dff to cell.\n");
return;
}
@@ -256,18 +256,18 @@ struct MemoryDffWorker
}
for (auto cell : module->cells()) {
- if (cell->type == "$dff")
+ if (cell->type == ID($dff))
dff_cells.push_back(cell);
- if (cell->type == "$mux") {
- mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
- mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
+ if (cell->type == ID($mux)) {
+ mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
+ mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
}
- if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_y = cell->getPort("\\Y");
- if (cell->type == "$not")
- sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
- if (cell->type == "$logic_not")
+ if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_y = cell->getPort(ID::Y);
+ if (cell->type == ID($not))
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+ if (cell->type == ID($logic_not))
sig_y.extend_u0(1);
for (int i = 0; i < GetSize(sig_y); i++)
invbits[sig_y[i]] = sig_a[i];
@@ -279,12 +279,12 @@ struct MemoryDffWorker
}
for (auto cell : module->selected_cells())
- if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_wr_cell(cell);
if (!flag_wr_only)
for (auto cell : module->selected_cells())
- if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_rd_cell(cell);
}
};
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 65bccb5ef..da0673c8f 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -81,15 +81,15 @@ struct MemoryMapWorker
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
- int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
- int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
+ int wr_ports = cell->parameters[ID::WR_PORTS].as_int();
+ int rd_ports = cell->parameters[ID::RD_PORTS].as_int();
- int mem_size = cell->parameters["\\SIZE"].as_int();
- int mem_width = cell->parameters["\\WIDTH"].as_int();
- int mem_offset = cell->parameters["\\OFFSET"].as_int();
- int mem_abits = cell->parameters["\\ABITS"].as_int();
+ int mem_size = cell->parameters[ID::SIZE].as_int();
+ int mem_width = cell->parameters[ID::WIDTH].as_int();
+ int mem_offset = cell->parameters[ID::OFFSET].as_int();
+ int mem_abits = cell->parameters[ID::ABITS].as_int();
- SigSpec init_data = cell->getParam("\\INIT");
+ SigSpec init_data = cell->getParam(ID::INIT);
init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell
@@ -99,22 +99,22 @@ struct MemoryMapWorker
}
// all write ports must share the same clock
- RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
- RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
- RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
+ RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
+ RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
+ RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
clocks_pol.bits.resize(wr_ports);
clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) {
- RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i);
continue;
}
if (clocks_en.bits[i] != RTLIL::State::S1) {
- RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width);
if (wr_addr.is_fully_const()) {
// FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en
@@ -155,21 +155,21 @@ struct MemoryMapWorker
}
else
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
- c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff));
+ c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
if (clocks_pol.bits.size() > 0) {
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
- c->setPort("\\CLK", clocks.extract(0, 1));
+ c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]);
+ c->setPort(ID::CLK, clocks.extract(0, 1));
} else {
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
- c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
+ c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
+ c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
}
RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
data_reg_in.push_back(RTLIL::SigSpec(w_in));
- c->setPort("\\D", data_reg_in.back());
+ c->setPort(ID::D, data_reg_in.back());
- std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
+ std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i);
if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q");
@@ -177,10 +177,10 @@ struct MemoryMapWorker
SigSpec w_init = init_data.extract(i*mem_width, mem_width);
if (!w_init.is_fully_undef())
- w_out->attributes["\\init"] = w_init.as_const();
+ w_out->attributes[ID::init] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out));
- c->setPort("\\Q", data_reg_out.back());
+ c->setPort(ID::Q, data_reg_out.back());
}
}
@@ -188,55 +188,55 @@ struct MemoryMapWorker
int count_dff = 0, count_mux = 0, count_wrmux = 0;
- for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
+ for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++)
{
- RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits);
if (mem_offset)
rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
std::vector<RTLIL::SigSpec> rd_signals;
- rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
+ rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width));
- if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
+ if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1)
{
RTLIL::Cell *dff_cell = nullptr;
- if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
+ if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1)
{
- dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
- dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- dff_cell->setPort("\\D", rd_addr);
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
+ dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits);
+ dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
+ dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
+ dff_cell->setPort(ID::D, rd_addr);
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
- dff_cell->setPort("\\Q", RTLIL::SigSpec(w));
+ dff_cell->setPort(ID::Q, RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w);
}
else
{
- dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- dff_cell->setPort("\\Q", rd_signals.back());
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
+ dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
+ dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
+ dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
+ dff_cell->setPort(ID::Q, rd_signals.back());
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w));
- dff_cell->setPort("\\D", rd_signals.back());
+ dff_cell->setPort(ID::D, rd_signals.back());
}
- SigBit en_bit = cell->getPort("\\RD_EN").extract(i);
+ SigBit en_bit = cell->getPort(ID::RD_EN).extract(i);
if (en_bit != State::S1) {
SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
- dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit);
- dff_cell->setPort("\\D", new_d);
+ dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit);
+ dff_cell->setPort(ID::D, new_d);
}
}
@@ -246,17 +246,17 @@ struct MemoryMapWorker
for (size_t k = 0; k < rd_signals.size(); k++)
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
- c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- c->setPort("\\Y", rd_signals[k]);
- c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1));
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux));
+ c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
+ c->setPort(ID::Y, rd_signals[k]);
+ c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
count_mux++;
- c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
- c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
+ c->setPort(ID::A, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
+ c->setPort(ID::B, module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
- next_rd_signals.push_back(c->getPort("\\A"));
- next_rd_signals.push_back(c->getPort("\\B"));
+ next_rd_signals.push_back(c->getPort(ID::A));
+ next_rd_signals.push_back(c->getPort(ID::B));
}
next_rd_signals.swap(rd_signals);
@@ -275,11 +275,11 @@ struct MemoryMapWorker
RTLIL::SigSpec sig = data_reg_out[i];
- for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
+ for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++)
{
- RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
- RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width);
if (mem_offset)
wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
@@ -303,27 +303,27 @@ struct MemoryMapWorker
if (wr_bit != State::S1)
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
- c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- c->setPort("\\A", w);
- c->setPort("\\B", wr_bit);
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and));
+ c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
+ c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
+ c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
+ c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
+ c->setPort(ID::A, w);
+ c->setPort(ID::B, wr_bit);
w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
- c->setPort("\\Y", RTLIL::SigSpec(w));
+ c->setPort(ID::Y, RTLIL::SigSpec(w));
}
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
- c->parameters["\\WIDTH"] = wr_width;
- c->setPort("\\A", sig.extract(wr_offset, wr_width));
- c->setPort("\\B", wr_data.extract(wr_offset, wr_width));
- c->setPort("\\S", RTLIL::SigSpec(w));
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux));
+ c->parameters[ID::WIDTH] = wr_width;
+ c->setPort(ID::A, sig.extract(wr_offset, wr_width));
+ c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
+ c->setPort(ID::S, RTLIL::SigSpec(w));
w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
- c->setPort("\\Y", w);
+ c->setPort(ID::Y, w);
sig.replace(wr_offset, w);
wr_offset += wr_width;
@@ -343,7 +343,7 @@ struct MemoryMapWorker
{
std::vector<RTLIL::Cell*> cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$mem" && design->selected(module, cell))
+ if (cell->type == ID($mem))
cells.push_back(cell);
for (auto cell : cells)
handle_cell(cell);
diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc
index 958370164..5d5f61c7d 100644
--- a/passes/memory/memory_memx.cc
+++ b/passes/memory/memory_memx.cc
@@ -47,18 +47,18 @@ struct MemoryMemxPass : public Pass {
vector<Cell*> mem_port_cells;
for (auto cell : module->selected_cells())
- if (cell->type.in("$memrd", "$memwr"))
+ if (cell->type.in(ID($memrd), ID($memwr)))
mem_port_cells.push_back(cell);
for (auto cell : mem_port_cells)
{
- IdString memid = cell->getParam("\\MEMID").decode_string();
+ IdString memid = cell->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
int lowest_addr = mem->start_offset;
int highest_addr = mem->start_offset + mem->size - 1;
- SigSpec addr = cell->getPort("\\ADDR");
+ SigSpec addr = cell->getPort(ID::ADDR);
addr.extend_u0(32);
SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1}));
@@ -66,23 +66,23 @@ struct MemoryMemxPass : public Pass {
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr));
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr));
- if (cell->type == "$memrd")
+ if (cell->type == ID($memrd))
{
- if (cell->getParam("\\CLK_ENABLE").as_bool())
+ if (cell->getParam(ID::CLK_ENABLE).as_bool())
log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n",
log_id(module), log_id(cell), log_id(cell->type));
- SigSpec rdata = cell->getPort("\\DATA");
+ SigSpec rdata = cell->getPort(ID::DATA);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata);
- cell->setPort("\\DATA", raw_rdata);
+ cell->setPort(ID::DATA, raw_rdata);
}
- if (cell->type == "$memwr")
+ if (cell->type == ID($memwr))
{
- SigSpec en = cell->getPort("\\EN");
+ SigSpec en = cell->getPort(ID::EN);
en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en)));
- cell->setPort("\\EN", en);
+ cell->setPort(ID::EN, en);
}
}
}
diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc
index ba0361c0f..487785397 100644
--- a/passes/memory/memory_nordff.cc
+++ b/passes/memory/memory_nordff.cc
@@ -52,19 +52,19 @@ struct MemoryNordffPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type != "$mem")
+ if (cell->type != ID($mem))
continue;
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- SigSpec rd_addr = cell->getPort("\\RD_ADDR");
- SigSpec rd_data = cell->getPort("\\RD_DATA");
- SigSpec rd_clk = cell->getPort("\\RD_CLK");
- SigSpec rd_en = cell->getPort("\\RD_EN");
- Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE");
- Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY");
+ SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
+ SigSpec rd_data = cell->getPort(ID::RD_DATA);
+ SigSpec rd_clk = cell->getPort(ID::RD_CLK);
+ SigSpec rd_en = cell->getPort(ID::RD_EN);
+ Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
+ Const rd_clk_polarity = cell->getParam(ID::RD_CLK_POLARITY);
for (int i = 0; i < rd_ports; i++)
{
@@ -72,11 +72,11 @@ struct MemoryNordffPass : public Pass {
if (clk_enable)
{
- bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1;
- bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1;
+ bool clk_polarity = cell->getParam(ID::RD_CLK_POLARITY)[i] == State::S1;
+ bool transparent = cell->getParam(ID::RD_TRANSPARENT)[i] == State::S1;
- SigSpec clk = cell->getPort("\\RD_CLK")[i] ;
- SigSpec en = cell->getPort("\\RD_EN")[i];
+ SigSpec clk = cell->getPort(ID::RD_CLK)[i] ;
+ SigSpec en = cell->getPort(ID::RD_EN)[i];
Cell *c;
if (transparent)
@@ -108,12 +108,12 @@ struct MemoryNordffPass : public Pass {
rd_clk_polarity[i] = State::S1;
}
- cell->setPort("\\RD_ADDR", rd_addr);
- cell->setPort("\\RD_DATA", rd_data);
- cell->setPort("\\RD_CLK", rd_clk);
- cell->setPort("\\RD_EN", rd_en);
- cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable);
- cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity);
+ cell->setPort(ID::RD_ADDR, rd_addr);
+ cell->setPort(ID::RD_DATA, rd_data);
+ cell->setPort(ID::RD_CLK, rd_clk);
+ cell->setPort(ID::RD_EN, rd_en);
+ cell->setParam(ID::RD_CLK_ENABLE, rd_clk_enable);
+ cell->setParam(ID::RD_CLK_POLARITY, rd_clk_polarity);
}
}
} MemoryNordffPass;
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index b33882595..477246687 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -27,11 +27,11 @@ PRIVATE_NAMESPACE_BEGIN
bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
- if (a->type == "$memrd" && b->type == "$memrd")
+ if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name;
- if (a->type == "$memrd" || b->type == "$memrd")
- return (a->type == "$memrd") < (b->type == "$memrd");
- return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
+ if (a->type == ID($memrd) || b->type == ID($memrd))
+ return (a->type == ID($memrd)) < (b->type == ID($memrd));
+ return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
}
struct MemoryShareWorker
@@ -64,18 +64,18 @@ struct MemoryShareWorker
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
int bit_idx = sig_to_mux.at(sig).second;
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
log_assert(sig_y.at(bit_idx) == sig);
for (int i = 0; i < int(sig_s.size()); i++)
if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->setPort("\\B", new_b);
+ cell->setPort(ID::B, new_b);
}
return false;
}
@@ -90,9 +90,9 @@ struct MemoryShareWorker
new_state[sig_s[i]] = true;
if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
- cell->setPort("\\B", new_b);
+ cell->setPort(ID::B, new_b);
}
}
@@ -101,9 +101,9 @@ struct MemoryShareWorker
new_state[sig_s[i]] = false;
if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
- RTLIL::SigSpec new_a = cell->getPort("\\A");
+ RTLIL::SigSpec new_a = cell->getPort(ID::A);
new_a.replace(bit_idx, RTLIL::State::Sx);
- cell->setPort("\\A", new_a);
+ cell->setPort(ID::A, new_a);
}
return false;
@@ -155,12 +155,12 @@ struct MemoryShareWorker
{
bool ignore_data_port = false;
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
- std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
- std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
non_feedback_nets.insert(sig_s.begin(), sig_s.end());
@@ -173,13 +173,13 @@ struct MemoryShareWorker
continue;
}
- if (cell->type.in("$memwr", "$memrd") &&
- cell->parameters.at("\\MEMID").decode_string() == memid)
+ if (cell->type.in(ID($memwr), ID($memrd)) &&
+ cell->parameters.at(ID::MEMID).decode_string() == memid)
ignore_data_port = true;
for (auto conn : cell->connections())
{
- if (ignore_data_port && conn.first == "\\DATA")
+ if (ignore_data_port && conn.first == ID::DATA)
continue;
std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
non_feedback_nets.insert(bits.begin(), bits.end());
@@ -204,11 +204,11 @@ struct MemoryShareWorker
for (auto cell : rd_ports)
{
- if (cell->parameters.at("\\CLK_ENABLE").as_bool())
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
- RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR"));
- std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA"));
+ RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR));
+ std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA));
for (int i = 0; i < int(sig_data.size()); i++)
if (non_feedback_nets.count(sig_data[i]))
@@ -228,14 +228,14 @@ struct MemoryShareWorker
for (auto cell : wr_ports)
{
- RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR"));
+ RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR));
if (!async_rd_bits.count(sig_addr))
continue;
log(" Analyzing write port %s.\n", log_id(cell));
- std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA");
- std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN");
+ std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN);
int created_conditions = 0;
for (int i = 0; i < int(cell_data.size()); i++)
@@ -250,7 +250,7 @@ struct MemoryShareWorker
if (created_conditions) {
log(" Added enable logic for %d different cases.\n", created_conditions);
- cell->setPort("\\EN", cell_en);
+ cell->setPort(ID::EN, cell_en);
}
}
}
@@ -368,15 +368,15 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++)
{
RTLIL::Cell *cell = wr_ports.at(i);
- RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR"));
+ RTLIL::SigSpec addr = sigmap_xmux(cell->getPort(ID::ADDR));
- if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
- cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
+ (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
+ cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{
- cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
- cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->getPort("\\CLK"));
+ cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
+ cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ cache_clk = sigmap(cell->getPort(ID::CLK));
last_port_by_addr.clear();
if (cache_clk_enable)
@@ -388,7 +388,7 @@ struct MemoryShareWorker
log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--) {
active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
@@ -410,13 +410,13 @@ struct MemoryShareWorker
// Force this ports addr input to addr directly (skip don't care muxes)
- cell->setPort("\\ADDR", addr);
+ cell->setPort(ID::ADDR, addr);
// If any of the ports between `last_i' and `i' write to the same address, this
// will have priority over whatever `last_i` wrote. So we need to revisit those
// ports and mask the EN bits accordingly.
- RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN"));
+ RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort(ID::EN));
for (int j = last_i+1; j < i; j++)
{
@@ -431,20 +431,20 @@ struct MemoryShareWorker
found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j);
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
- module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr);
- merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN")));
+ module->addEq(NEW_ID, addr, wr_ports[j]->getPort(ID::ADDR), is_same_addr);
+ merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort(ID::EN)));
}
}
// Then we need to merge the (masked) EN and the DATA signals.
- RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA");
+ RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort(ID::DATA);
if (found_overlapping_bits) {
log(" Creating logic for merging DATA and EN ports.\n");
- merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA")));
+ merge_en_data(merged_en, merged_data, sigmap(cell->getPort(ID::EN)), sigmap(cell->getPort(ID::DATA)));
} else {
- RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN"));
- RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA"));
+ RTLIL::SigSpec cell_en = sigmap(cell->getPort(ID::EN));
+ RTLIL::SigSpec cell_data = sigmap(cell->getPort(ID::DATA));
for (int k = 0; k < int(en_bits.size()); k++)
if (!active_bits_on_port[last_i][k]) {
merged_en.replace(k, cell_en.extract(k, 1));
@@ -454,14 +454,14 @@ struct MemoryShareWorker
// Connect the new EN and DATA signals and remove the old write port.
- cell->setPort("\\EN", merged_en);
- cell->setPort("\\DATA", merged_data);
+ cell->setPort(ID::EN, merged_en);
+ cell->setPort(ID::DATA, merged_data);
module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL;
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--)
log("%c", active_bits_on_port[i][k] ? '1' : '0');
@@ -500,7 +500,7 @@ struct MemoryShareWorker
std::set<int> considered_port_pairs;
for (int i = 0; i < int(wr_ports.size()); i++) {
- std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
for (auto bit : bits)
if (bit == RTLIL::State::S1)
goto port_is_always_active;
@@ -519,13 +519,13 @@ struct MemoryShareWorker
{
RTLIL::Cell *cell = wr_ports.at(i);
- if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
- cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
+ (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
+ cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{
- cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
- cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->getPort("\\CLK"));
+ cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
+ cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ cache_clk = sigmap(cell->getPort(ID::CLK));
}
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
considered_port_pairs.insert(i);
@@ -554,7 +554,7 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++)
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
{
- RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
std::vector<RTLIL::SigBit> bits = sig;
@@ -564,7 +564,7 @@ struct MemoryShareWorker
while (!bits_queue.empty())
{
for (auto bit : bits_queue)
- if (bit.wire && bit.wire->get_bool_attribute("\\onehot"))
+ if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
one_hot_wires.insert(bit.wire);
pool<ModWalker::PortBit> portbits;
@@ -609,13 +609,13 @@ struct MemoryShareWorker
log(" Merging port %d into port %d.\n", i-1, i);
port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
- RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR");
- RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA");
- std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN"));
+ RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort(ID::ADDR);
+ RTLIL::SigSpec last_data = wr_ports[i-1]->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort(ID::EN));
- RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR");
- RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA");
- std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ RTLIL::SigSpec this_addr = wr_ports[i]->getPort(ID::ADDR);
+ RTLIL::SigSpec this_data = wr_ports[i]->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
@@ -624,9 +624,9 @@ struct MemoryShareWorker
else
this_addr.extend_u0(GetSize(last_addr));
- wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
- wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
- wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
+ wr_ports[i]->setParam(ID::ABITS, GetSize(this_addr));
+ wr_ports[i]->setPort(ID::ADDR, module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
+ wr_ports[i]->setPort(ID::DATA, module->Mux(NEW_ID, last_data, this_data, this_en_active));
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@@ -644,7 +644,7 @@ struct MemoryShareWorker
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
- wr_ports[i]->setPort("\\EN", en);
+ wr_ports[i]->setPort(ID::EN, en);
module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL;
@@ -679,26 +679,26 @@ struct MemoryShareWorker
sigmap_xmux = sigmap;
for (auto cell : module->cells())
{
- if (cell->type == "$memrd")
- memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
+ if (cell->type == ID($memrd))
+ memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell);
- if (cell->type == "$memwr")
- memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell);
+ if (cell->type == ID($memwr))
+ memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell);
- if (cell->type == "$mux")
+ if (cell->type == ID($mux))
{
- RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
if (sig_a.is_fully_undef())
- sigmap_xmux.add(cell->getPort("\\Y"), sig_b);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
else if (sig_b.is_fully_undef())
- sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
+ sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
}
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < int(sig_y.size()); i++)
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
}
@@ -712,16 +712,16 @@ struct MemoryShareWorker
}
cone_ct.setup_internals();
- cone_ct.cell_types.erase("$mul");
- cone_ct.cell_types.erase("$mod");
- cone_ct.cell_types.erase("$div");
- cone_ct.cell_types.erase("$pow");
- cone_ct.cell_types.erase("$shl");
- cone_ct.cell_types.erase("$shr");
- cone_ct.cell_types.erase("$sshl");
- cone_ct.cell_types.erase("$sshr");
- cone_ct.cell_types.erase("$shift");
- cone_ct.cell_types.erase("$shiftx");
+ cone_ct.cell_types.erase(ID($mul));
+ cone_ct.cell_types.erase(ID($mod));
+ cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($pow));
+ cone_ct.cell_types.erase(ID($shl));
+ cone_ct.cell_types.erase(ID($shr));
+ cone_ct.cell_types.erase(ID($sshl));
+ cone_ct.cell_types.erase(ID($sshr));
+ cone_ct.cell_types.erase(ID($shift));
+ cone_ct.cell_types.erase(ID($shiftx));
modwalker.setup(module, &cone_ct);
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 49ec66792..9173c791b 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -31,53 +31,53 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str());
- RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
+ RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at(ID::MEMID).decode_string());
while (module->memories.count(mem_name) != 0)
mem_name = mem_name.str() + stringf("_%d", autoidx++);
RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = mem_name;
- mem->width = memory->parameters.at("\\WIDTH").as_int();
- mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
- mem->size = memory->parameters.at("\\SIZE").as_int();
+ mem->width = memory->parameters.at(ID::WIDTH).as_int();
+ mem->start_offset = memory->parameters.at(ID::OFFSET).as_int();
+ mem->size = memory->parameters.at(ID::SIZE).as_int();
module->memories[mem_name] = mem;
- int abits = memory->parameters.at("\\ABITS").as_int();
- int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
- int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
+ int abits = memory->parameters.at(ID::ABITS).as_int();
+ int num_rd_ports = memory->parameters.at(ID::RD_PORTS).as_int();
+ int num_wr_ports = memory->parameters.at(ID::WR_PORTS).as_int();
for (int i = 0; i < num_rd_ports; i++)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
- cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
- cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
- cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
- cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1));
- cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
- cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memrd));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_ENABLE)).extract(i, 1).as_const();
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_POLARITY)).extract(i, 1).as_const();
+ cell->parameters[ID::TRANSPARENT] = RTLIL::SigSpec(memory->parameters.at(ID::RD_TRANSPARENT)).extract(i, 1).as_const();
+ cell->setPort(ID::CLK, memory->getPort(ID::RD_CLK).extract(i, 1));
+ cell->setPort(ID::EN, memory->getPort(ID::RD_EN).extract(i, 1));
+ cell->setPort(ID::ADDR, memory->getPort(ID::RD_ADDR).extract(i*abits, abits));
+ cell->setPort(ID::DATA, memory->getPort(ID::RD_DATA).extract(i*mem->width, mem->width));
}
for (int i = 0; i < num_wr_ports; i++)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
- cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
- cell->parameters["\\PRIORITY"] = i;
- cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
- cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
- cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
- cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memwr));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_ENABLE)).extract(i, 1).as_const();
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_POLARITY)).extract(i, 1).as_const();
+ cell->parameters[ID::PRIORITY] = i;
+ cell->setPort(ID::CLK, memory->getPort(ID::WR_CLK).extract(i, 1));
+ cell->setPort(ID::EN, memory->getPort(ID::WR_EN).extract(i*mem->width, mem->width));
+ cell->setPort(ID::ADDR, memory->getPort(ID::WR_ADDR).extract(i*abits, abits));
+ cell->setPort(ID::DATA, memory->getPort(ID::WR_DATA).extract(i*mem->width, mem->width));
}
- Const initval = memory->parameters.at("\\INIT");
+ Const initval = memory->parameters.at(ID::INIT);
RTLIL::Cell *last_init_cell = nullptr;
SigSpec last_init_data;
int last_init_addr=0;
@@ -90,19 +90,19 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
continue;
found_non_undef_initval:
if (last_init_cell && last_init_addr+1 == i/mem->width) {
- last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1;
+ last_init_cell->parameters[ID::WORDS] = last_init_cell->parameters[ID::WORDS].as_int() + 1;
last_init_data.append(val);
last_init_addr++;
} else {
if (last_init_cell)
- last_init_cell->setPort("\\DATA", last_init_data);
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\WORDS"] = 1;
- cell->parameters["\\PRIORITY"] = i/mem->width;
- cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
+ last_init_cell->setPort(ID::DATA, last_init_data);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($meminit));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::WORDS] = 1;
+ cell->parameters[ID::PRIORITY] = i/mem->width;
+ cell->setPort(ID::ADDR, SigSpec(i/mem->width, abits));
last_init_cell = cell;
last_init_addr = i/mem->width;
last_init_data = val;
@@ -110,7 +110,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
}
if (last_init_cell)
- last_init_cell->setPort("\\DATA", last_init_data);
+ last_init_cell->setPort(ID::DATA, last_init_data);
module->remove(memory);
}
@@ -119,7 +119,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::IdString> memcells;
for (auto &cell_it : module->cells_)
- if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
+ if (cell_it.second->type == ID($mem) && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first);
for (auto &it : memcells)
handle_memory(module, module->cells_.at(it));
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 07:11:30 +0000