aboutsummaryrefslogtreecommitdiffstats
path: root/passes/memory
diff options
context:
space:
mode:
Diffstat (limited to 'passes/memory')
-rw-r--r--passes/memory/memory.cc19
-rw-r--r--passes/memory/memory_bram.cc126
-rw-r--r--passes/memory/memory_collect.cc245
-rw-r--r--passes/memory/memory_dff.cc347
-rw-r--r--passes/memory/memory_map.cc68
-rw-r--r--passes/memory/memory_share.cc68
-rw-r--r--passes/memory/memory_unpack.cc44
7 files changed, 590 insertions, 327 deletions
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index 866efae77..e3c627607 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -31,11 +31,11 @@ struct MemoryPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" memory [-nomap] [-bram <bram_rules>] [selection]\n");
+ log(" memory [-nomap] [-nordff] [-bram <bram_rules>] [selection]\n");
log("\n");
log("This pass calls all the other memory_* passes in a useful order:\n");
log("\n");
- log(" memory_dff\n");
+ log(" memory_dff [-nordff]\n");
log(" opt_clean\n");
log(" memory_share\n");
log(" opt_clean\n");
@@ -50,9 +50,10 @@ struct MemoryPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
bool flag_nomap = false;
+ bool flag_nordff = false;
string memory_bram_opts;
- log_header("Executing MEMORY pass.\n");
+ log_header(design, "Executing MEMORY pass.\n");
log_push();
size_t argidx;
@@ -61,6 +62,10 @@ struct MemoryPass : public Pass {
flag_nomap = true;
continue;
}
+ if (args[argidx] == "-nordff") {
+ flag_nordff = true;
+ continue;
+ }
if (argidx+1 < args.size() && args[argidx] == "-bram") {
memory_bram_opts += " -rules " + args[++argidx];
continue;
@@ -69,7 +74,7 @@ struct MemoryPass : public Pass {
}
extra_args(args, argidx, design);
- Pass::call(design, "memory_dff");
+ Pass::call(design, flag_nordff ? "memory_dff -nordff" : "memory_dff");
Pass::call(design, "opt_clean");
Pass::call(design, "memory_share");
Pass::call(design, "opt_clean");
@@ -84,5 +89,5 @@ struct MemoryPass : public Pass {
log_pop();
}
} MemoryPass;
-
+
PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 8f4214027..7b5dd08ab 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -32,6 +32,7 @@ struct rules_t
SigSpec sig_addr, sig_data, sig_en;
bool effective_clkpol;
bool make_transp;
+ bool make_outreg;
int mapped_port;
};
@@ -85,6 +86,7 @@ struct rules_t
pi.clkpol = clkpol[i];
pi.mapped_port = -1;
pi.make_transp = false;
+ pi.make_outreg = false;
pi.effective_clkpol = false;
portinfos.push_back(pi);
}
@@ -110,15 +112,15 @@ struct rules_t
if (ports[i] != other.ports[i])
log_error("Bram %s variants %d and %d have different number of %c-ports.\n", log_id(name), variant, other.variant, 'A'+i);
if (wrmode[i] != other.wrmode[i])
- variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[1];
+ variant_params[stringf("\\CFG_WRMODE_%c", 'A' + i)] = wrmode[i];
if (enable[i] != other.enable[i])
- variant_params[stringf("\\CFG_ENABLE_%c", 'A' + i)] = enable[1];
+ variant_params[stringf("\\CFG_ENABLE_%c", 'A' + i)] = enable[i];
if (transp[i] != other.transp[i])
- variant_params[stringf("\\CFG_TRANSP_%c", 'A' + i)] = transp[1];
+ variant_params[stringf("\\CFG_TRANSP_%c", 'A' + i)] = transp[i];
if (clocks[i] != other.clocks[i])
- variant_params[stringf("\\CFG_CLOCKS_%c", 'A' + i)] = clocks[1];
+ variant_params[stringf("\\CFG_CLOCKS_%c", 'A' + i)] = clocks[i];
if (clkpol[i] != other.clkpol[i])
- variant_params[stringf("\\CFG_CLKPOL_%c", 'A' + i)] = clkpol[1];
+ variant_params[stringf("\\CFG_CLKPOL_%c", 'A' + i)] = clkpol[i];
}
}
};
@@ -126,7 +128,7 @@ struct rules_t
struct match_t {
IdString name;
dict<string, int> min_limits, max_limits;
- bool or_next_if_better, make_transp;
+ bool or_next_if_better, make_transp, make_outreg;
char shuffle_enable;
};
@@ -277,6 +279,7 @@ struct rules_t
data.name = RTLIL::escape_id(tokens[1]);
data.or_next_if_better = false;
data.make_transp = false;
+ data.make_outreg = false;
data.shuffle_enable = 0;
while (next_line())
@@ -309,6 +312,12 @@ struct rules_t
continue;
}
+ if (GetSize(tokens) == 1 && tokens[0] == "make_outreg") {
+ data.make_transp = true;
+ data.make_outreg = true;
+ continue;
+ }
+
if (GetSize(tokens) == 1 && tokens[0] == "or_next_if_better") {
data.or_next_if_better = true;
continue;
@@ -320,9 +329,7 @@ struct rules_t
void parse(string filename)
{
- if (filename.substr(0, 2) == "+/")
- filename = proc_share_dirname() + filename.substr(1);
-
+ rewrite_filename(filename);
infile.open(filename);
linecount = 0;
@@ -380,9 +387,9 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
if (pi.clkpol > 1)
clkpol_wr_ports.insert(pi.clkpol);
}
- clocks_max = std::max(clocks_max, pi.clocks);
- clkpol_max = std::max(clkpol_max, pi.clkpol);
- transp_max = std::max(transp_max, pi.transp);
+ clocks_max = max(clocks_max, pi.clocks);
+ clkpol_max = max(clkpol_max, pi.clkpol);
+ transp_max = max(transp_max, pi.transp);
}
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
@@ -393,6 +400,16 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
int mem_width = cell->getParam("\\WIDTH").as_int();
// int mem_offset = cell->getParam("\\OFFSET").as_int();
+ bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+ vector<Const> initdata;
+
+ if (cell_init) {
+ Const initparam = cell->getParam("\\INIT");
+ initdata.reserve(mem_size);
+ for (int i=0; i < mem_size; i++)
+ initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx));
+ }
+
int wr_ports = cell->getParam("\\WR_PORTS").as_int();
auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE"));
auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY"));
@@ -412,11 +429,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
rd_clkpol.extend_u0(rd_ports);
rd_transp.extend_u0(rd_ports);
+ SigSpec rd_en = cell->getPort("\\RD_EN");
SigSpec rd_clk = cell->getPort("\\RD_CLK");
SigSpec rd_data = cell->getPort("\\RD_DATA");
SigSpec rd_addr = cell->getPort("\\RD_ADDR");
- if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0)
+ if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
{
int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable;
log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);
@@ -588,7 +606,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
mapped_wr_port:;
}
- // houskeeping stuff for growing more read ports and restarting read port assignments
+ // housekeeping stuff for growing more read ports and restarting read port assignments
int grow_read_ports_cursor = -1;
bool try_growing_more_read_ports = false;
@@ -656,6 +674,10 @@ grow_read_ports:;
if (clken) {
if (pi.clocks == 0) {
+ if (match.make_outreg) {
+ pi.make_outreg = true;
+ goto skip_bram_rport_clkcheck;
+ }
log(" Bram port %c%d.%d has incompatible clock type.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
goto skip_bram_rport;
}
@@ -667,12 +689,17 @@ grow_read_ports:;
log(" Bram port %c%d.%d has incompatible clock polarity.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
goto skip_bram_rport;
}
+ if (rd_en[cell_port_i] != State::S1 && pi.enable == 0) {
+ log(" Bram port %c%d.%d has no read enable input.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+ goto skip_bram_rport;
+ }
+ skip_bram_rport_clkcheck:
if (read_transp.count(pi.transp) && read_transp.at(pi.transp) != transp) {
if (match.make_transp && wr_ports <= 1) {
pi.make_transp = true;
enable_make_transp = true;
} else {
- log(" Bram port %c%d.%d has incompatible read transparancy.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+ log(" Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
goto skip_bram_rport;
}
}
@@ -691,6 +718,7 @@ grow_read_ports:;
clock_polarities[pi.clkpol] = clkdom.second;
read_transp[pi.transp] = transp;
pi.sig_clock = clkdom.first;
+ pi.sig_en = rd_en[cell_port_i];
pi.effective_clkpol = clkdom.second;
}
@@ -789,6 +817,22 @@ grow_read_ports:;
for (auto &vp : variant_params)
c->setParam(vp.first, vp.second);
+ if (cell_init) {
+ int init_offset = grid_a*(1 << bram.abits);
+ int init_shift = grid_d*bram.dbits;
+ int init_size = (1 << bram.abits);
+ Const initparam(State::Sx, init_size*bram.dbits);
+ for (int i = 0; i < init_size; i++) {
+ State padding = State::Sx;
+ for (int j = 0; j < bram.dbits; j++)
+ if (init_offset+i < GetSize(initdata) && init_shift+j < GetSize(initdata[init_offset+i]))
+ initparam[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
+ else
+ initparam[i*bram.dbits+j] = padding;
+ }
+ c->setParam("\\INIT", initparam);
+ }
+
for (auto &pi : portinfos)
{
if (pi.dupidx != dupidx)
@@ -815,8 +859,11 @@ grow_read_ports:;
if (pi.enable)
{
SigSpec sig_en = pi.sig_en;
- sig_en.extend_u0((grid_d+1) * pi.enable);
- sig_en = sig_en.extract(grid_d * pi.enable, pi.enable);
+
+ if (pi.wrmode == 1) {
+ sig_en.extend_u0((grid_d+1) * pi.enable);
+ sig_en = sig_en.extract(grid_d * pi.enable, pi.enable);
+ }
if (!addr_ok.empty())
sig_en = module->Mux(NEW_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok);
@@ -846,6 +893,14 @@ grow_read_ports:;
SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
c->setPort(stringf("\\%sDATA", pf), bram_dout);
+ if (pi.make_outreg) {
+ SigSpec bram_dout_q = module->addWire(NEW_ID, bram.dbits);
+ if (!pi.sig_en.empty())
+ bram_dout = module->Mux(NEW_ID, bram_dout_q, bram_dout, pi.sig_en);
+ module->addDff(NEW_ID, pi.sig_clock, bram_dout, bram_dout_q, pi.effective_clkpol);
+ bram_dout = bram_dout_q;
+ }
+
if (pi.make_transp)
{
log(" Adding extra logic for transparent port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
@@ -871,7 +926,7 @@ grow_read_ports:;
}
SigSpec addr_ok_q = addr_ok;
- if (pi.clocks && !addr_ok.empty()) {
+ if ((pi.clocks || pi.make_outreg) && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol);
}
@@ -905,6 +960,8 @@ void handle_cell(Cell *cell, const rules_t &rules)
{
log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
+ bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+
dict<string, int> match_properties;
match_properties["words"] = cell->getParam("\\SIZE").as_int();
match_properties["abits"] = cell->getParam("\\ABITS").as_int();
@@ -920,7 +977,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
log("\n");
pool<pair<IdString, int>> failed_brams;
- dict<pair<int, int>, std::tuple<int, int, int>> best_rule_cache;
+ dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;
for (int i = 0; i < GetSize(rules.matches); i++)
{
@@ -975,6 +1032,12 @@ void handle_cell(Cell *cell, const rules_t &rules)
log(" Metrics for %s: awaste=%d dwaste=%d bwaste=%d waste=%d efficiency=%d\n",
log_id(match.name), awaste, dwaste, bwaste, waste, efficiency);
+ if (cell_init && bram.init == 0) {
+ log(" Rule #%d for bram type %s (variant %d) rejected: cannot be initialized.\n",
+ i+1, log_id(bram.name), bram.variant);
+ goto next_match_rule;
+ }
+
for (auto it : match.min_limits) {
if (it.first == "waste" || it.first == "dups" || it.first == "acells" || it.first == "dcells" || it.first == "cells")
continue;
@@ -987,6 +1050,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
i+1, log_id(bram.name), bram.variant, it.first.c_str(), it.second);
goto next_match_rule;
}
+
for (auto it : match.max_limits) {
if (it.first == "acells" || it.first == "dcells" || it.first == "cells")
continue;
@@ -1014,10 +1078,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
}
log(" Storing for later selection.\n");
- best_rule_cache[pair<int, int>(i, vi)] = std::tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
-
- if (or_next_if_better)
- goto next_match_rule;
+ best_rule_cache[pair<int, int>(i, vi)] = tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]);
next_match_rule:
if (or_next_if_better || best_rule_cache.empty())
@@ -1070,14 +1131,14 @@ struct MemoryBramPass : public Pass {
log("rules. A block ram description looks like this:\n");
log("\n");
log(" bram RAMB1024X32 # name of BRAM cell\n");
- // log(" init 1 # set to '1' if BRAM can be initialized\n");
+ log(" init 1 # set to '1' if BRAM can be initialized\n");
log(" abits 10 # number of address bits\n");
log(" dbits 32 # number of data bits\n");
log(" groups 2 # number of port groups\n");
log(" ports 1 1 # number of ports in each group\n");
log(" wrmode 1 0 # set to '1' if this groups is write ports\n");
- log(" enable 4 0 # number of enable bits (for write ports)\n");
- log(" transp 0 2 # transparatent (for read ports)\n");
+ log(" enable 4 1 # number of enable bits\n");
+ log(" transp 0 2 # transparent (for read ports)\n");
log(" clocks 1 2 # clock configuration\n");
log(" clkpol 2 2 # clock polarity configuration\n");
log(" endbram\n");
@@ -1095,7 +1156,7 @@ struct MemoryBramPass : public Pass {
log("greater than 1 share the same configuration bit.\n");
log("\n");
log("Using the same bram name in different bram blocks will create different variants\n");
- log("of the bram. Verilog configration parameters for the bram are created as needed.\n");
+ log("of the bram. Verilog configuration parameters for the bram are created as needed.\n");
log("\n");
log("It is also possible to create variants by repeating statements in the bram block\n");
log("and appending '@<label>' to the individual statements.\n");
@@ -1128,7 +1189,7 @@ struct MemoryBramPass : public Pass {
log(" dcells ....... number of cells in 'data-direction'\n");
log(" cells ........ total number of cells (acells*dcells*dups)\n");
log("\n");
- log("The interface for the created bram instances is dervived from the bram\n");
+ log("The interface for the created bram instances is derived from the bram\n");
log("description. Use 'techmap' to convert the created bram instances into\n");
log("instances of the actual bram cells of your target architecture.\n");
log("\n");
@@ -1139,6 +1200,9 @@ struct MemoryBramPass : public Pass {
log("A match containing the command 'make_transp' will add external circuitry\n");
log("to simulate 'transparent read', if necessary.\n");
log("\n");
+ log("A match containing the command 'make_outreg' will add external flip-flops\n");
+ log("to implement synchronous read ports, if necessary.\n");
+ log("\n");
log("A match containing the command 'shuffle_enable A' will re-organize\n");
log("the data bits to accommodate the enable pattern of port A.\n");
log("\n");
@@ -1147,7 +1211,7 @@ struct MemoryBramPass : public Pass {
{
rules_t rules;
- log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
+ log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index ccc196202..e068ef905 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -17,16 +17,13 @@
*
*/
-#include "kernel/register.h"
-#include "kernel/log.h"
-#include <sstream>
-#include <algorithm>
-#include <stdlib.h>
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+bool memcells_cmp(Cell *a, Cell *b)
{
if (a->type == "$memrd" && b->type == "$memrd")
return a->name < b->name;
@@ -35,108 +32,152 @@ bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
}
-void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
+Cell *handle_memory(Module *module, RTLIL::Memory *memory)
{
- log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
+ log("Collecting $memrd, $memwr and $meminit for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str());
int addr_bits = 0;
- while ((1 << addr_bits) < memory->size)
- addr_bits++;
+
+ Const init_data(State::Sx, memory->size * memory->width);
+ SigMap sigmap(module);
int wr_ports = 0;
- RTLIL::SigSpec sig_wr_clk;
- RTLIL::SigSpec sig_wr_clk_enable;
- RTLIL::SigSpec sig_wr_clk_polarity;
- RTLIL::SigSpec sig_wr_addr;
- RTLIL::SigSpec sig_wr_data;
- RTLIL::SigSpec sig_wr_en;
+ SigSpec sig_wr_clk;
+ SigSpec sig_wr_clk_enable;
+ SigSpec sig_wr_clk_polarity;
+ SigSpec sig_wr_addr;
+ SigSpec sig_wr_data;
+ SigSpec sig_wr_en;
int rd_ports = 0;
- RTLIL::SigSpec sig_rd_clk;
- RTLIL::SigSpec sig_rd_clk_enable;
- RTLIL::SigSpec sig_rd_clk_polarity;
- RTLIL::SigSpec sig_rd_transparent;
- RTLIL::SigSpec sig_rd_addr;
- RTLIL::SigSpec sig_rd_data;
+ SigSpec sig_rd_clk;
+ SigSpec sig_rd_clk_enable;
+ SigSpec sig_rd_clk_polarity;
+ SigSpec sig_rd_transparent;
+ SigSpec sig_rd_addr;
+ SigSpec sig_rd_data;
+ SigSpec sig_rd_en;
- std::vector<RTLIL::Cell*> del_cells;
- std::vector<RTLIL::Cell*> memcells;
+ std::vector<Cell*> memcells;
for (auto &cell_it : module->cells_) {
- RTLIL::Cell *cell = cell_it.second;
- if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string())
+ Cell *cell = cell_it.second;
+ if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
+ addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int());
memcells.push_back(cell);
+ }
+ }
+
+ if (memcells.empty()) {
+ log(" no cells found. removing memory.\n");
+ return nullptr;
}
std::sort(memcells.begin(), memcells.end(), memcells_cmp);
for (auto cell : memcells)
{
- if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string())
+ log(" %s (%s)\n", log_id(cell), log_id(cell->type));
+
+ if (cell->type == "$meminit")
{
- wr_ports++;
- del_cells.push_back(cell);
-
- RTLIL::SigSpec clk = cell->getPort("\\CLK");
- RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
- RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
- RTLIL::SigSpec addr = cell->getPort("\\ADDR");
- RTLIL::SigSpec data = cell->getPort("\\DATA");
- RTLIL::SigSpec en = cell->getPort("\\EN");
-
- clk.extend_u0(1, false);
- clk_enable.extend_u0(1, false);
- clk_polarity.extend_u0(1, false);
- addr.extend_u0(addr_bits, false);
- data.extend_u0(memory->width, false);
- en.extend_u0(memory->width, false);
-
- sig_wr_clk.append(clk);
- sig_wr_clk_enable.append(clk_enable);
- sig_wr_clk_polarity.append(clk_polarity);
- sig_wr_addr.append(addr);
- sig_wr_data.append(data);
- sig_wr_en.append(en);
+ SigSpec addr = sigmap(cell->getPort("\\ADDR"));
+ SigSpec data = sigmap(cell->getPort("\\DATA"));
+
+ if (!addr.is_fully_const())
+ log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
+ if (!data.is_fully_const())
+ log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), log_id(cell));
+
+ int offset = (addr.as_int() - memory->start_offset) * memory->width;
+
+ if (offset < 0 || offset + GetSize(data) > GetSize(init_data))
+ log_warning("Address %s in memory initialization %s is out-of-bounds.\n", log_signal(addr), log_id(cell));
+
+ for (int i = 0; i < GetSize(data); i++)
+ if (0 <= i+offset && i+offset < GetSize(init_data))
+ init_data.bits[i+offset] = data[i].data;
+
+ continue;
}
- if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string())
+ if (cell->type == "$memwr")
{
- rd_ports++;
- del_cells.push_back(cell);
-
- RTLIL::SigSpec clk = cell->getPort("\\CLK");
- RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
- RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
- RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
- RTLIL::SigSpec addr = cell->getPort("\\ADDR");
- RTLIL::SigSpec data = cell->getPort("\\DATA");
-
- clk.extend_u0(1, false);
- clk_enable.extend_u0(1, false);
- clk_polarity.extend_u0(1, false);
- transparent.extend_u0(1, false);
- addr.extend_u0(addr_bits, false);
- data.extend_u0(memory->width, false);
-
- sig_rd_clk.append(clk);
- sig_rd_clk_enable.append(clk_enable);
- sig_rd_clk_polarity.append(clk_polarity);
- sig_rd_transparent.append(transparent);
- sig_rd_addr.append(addr);
- sig_rd_data.append(data);
+ SigSpec clk = sigmap(cell->getPort("\\CLK"));
+ SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
+ SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
+ SigSpec addr = sigmap(cell->getPort("\\ADDR"));
+ SigSpec data = sigmap(cell->getPort("\\DATA"));
+ SigSpec en = sigmap(cell->getPort("\\EN"));
+
+ if (!en.is_fully_zero())
+ {
+ clk.extend_u0(1, false);
+ clk_enable.extend_u0(1, false);
+ clk_polarity.extend_u0(1, false);
+ addr.extend_u0(addr_bits, false);
+ data.extend_u0(memory->width, false);
+ en.extend_u0(memory->width, false);
+
+ sig_wr_clk.append(clk);
+ sig_wr_clk_enable.append(clk_enable);
+ sig_wr_clk_polarity.append(clk_polarity);
+ sig_wr_addr.append(addr);
+ sig_wr_data.append(data);
+ sig_wr_en.append(en);
+
+ wr_ports++;
+ }
+ continue;
+ }
+
+ if (cell->type == "$memrd")
+ {
+ SigSpec clk = sigmap(cell->getPort("\\CLK"));
+ SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
+ SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
+ SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]);
+ SigSpec addr = sigmap(cell->getPort("\\ADDR"));
+ SigSpec data = sigmap(cell->getPort("\\DATA"));
+ SigSpec en = sigmap(cell->getPort("\\EN"));
+
+ if (!en.is_fully_zero())
+ {
+ clk.extend_u0(1, false);
+ clk_enable.extend_u0(1, false);
+ clk_polarity.extend_u0(1, false);
+ transparent.extend_u0(1, false);
+ addr.extend_u0(addr_bits, false);
+ data.extend_u0(memory->width, false);
+
+ sig_rd_clk.append(clk);
+ sig_rd_clk_enable.append(clk_enable);
+ sig_rd_clk_polarity.append(clk_polarity);
+ sig_rd_transparent.append(transparent);
+ sig_rd_addr.append(addr);
+ sig_rd_data.append(data);
+ sig_rd_en.append(en);
+
+ rd_ports++;
+ }
+ continue;
}
}
std::stringstream sstr;
sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
- RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
- mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
- mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
- mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
- mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
- mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
+ Cell *mem = module->addCell(sstr.str(), "$mem");
+ mem->parameters["\\MEMID"] = Const(memory->name.str());
+ mem->parameters["\\WIDTH"] = Const(memory->width);
+ mem->parameters["\\OFFSET"] = Const(memory->start_offset);
+ mem->parameters["\\SIZE"] = Const(memory->size);
+ mem->parameters["\\ABITS"] = Const(addr_bits);
+
+ while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx)
+ init_data.bits.pop_back();
+ mem->parameters["\\INIT"] = init_data;
log_assert(sig_wr_clk.size() == wr_ports);
log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
@@ -145,9 +186,9 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
log_assert(sig_wr_data.size() == wr_ports * memory->width);
log_assert(sig_wr_en.size() == wr_ports * memory->width);
- mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_PORTS"] = Const(wr_ports);
+ mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : Const(0, 1);
+ mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : Const(0, 1);
mem->setPort("\\WR_CLK", sig_wr_clk);
mem->setPort("\\WR_ADDR", sig_wr_addr);
@@ -160,30 +201,36 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
log_assert(sig_rd_data.size() == rd_ports * memory->width);
- mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_PORTS"] = Const(rd_ports);
+ mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : Const(0, 1);
+ mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : Const(0, 1);
+ mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : Const(0, 1);
mem->setPort("\\RD_CLK", sig_rd_clk);
mem->setPort("\\RD_ADDR", sig_rd_addr);
mem->setPort("\\RD_DATA", sig_rd_data);
+ mem->setPort("\\RD_EN", sig_rd_en);
- for (auto c : del_cells)
+ for (auto c : memcells)
module->remove(c);
+
+ return mem;
}
-static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
+static void handle_module(Design *design, Module *module)
{
- std::vector<RTLIL::IdString> delme;
+ std::vector<pair<Cell*, IdString>> finqueue;
+
for (auto &mem_it : module->memories)
if (design->selected(module, mem_it.second)) {
- handle_memory(module, mem_it.second);
- delme.push_back(mem_it.first);
+ Cell *c = handle_memory(module, mem_it.second);
+ finqueue.push_back(pair<Cell*, IdString>(c, mem_it.first));
}
- for (auto &it : delme) {
- delete module->memories.at(it);
- module->memories.erase(it);
+ for (auto &it : finqueue) {
+ delete module->memories.at(it.second);
+ module->memories.erase(it.second);
+ if (it.first)
+ module->rename(it.first, it.second);
}
}
@@ -200,12 +247,12 @@ struct MemoryCollectPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
- log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
+ log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
} MemoryCollectPass;
-
+
PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index d3cc681a2..40691d160 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -17,170 +17,251 @@
*
*/
-#include "kernel/register.h"
-#include "kernel/log.h"
-#include <stdlib.h>
-#include <sstream>
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
+struct MemoryDffWorker
{
- for (auto &conn : module->connections())
- sig.replace(conn.first, conn.second);
-}
+ Module *module;
+ SigMap sigmap;
-bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
-{
- normalize_sig(module, sig);
+ vector<Cell*> dff_cells;
+ dict<SigBit, SigBit> invbits;
+ dict<SigBit, int> sigbit_users_count;
+ dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
+ pool<Cell*> forward_merged_dffs, candidate_dffs;
+
+ MemoryDffWorker(Module *module) : module(module), sigmap(module) { }
- for (auto &bit : sig)
+ bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
{
- if (bit.wire == NULL)
- continue;
+ sigmap.apply(sig);
- for (auto cell : dff_cells)
+ for (auto &bit : sig)
{
- if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
- if (cell->getPort("\\CLK") != clk)
- continue;
- if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
- continue;
- }
-
- RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
- normalize_sig(module, q_norm);
-
- RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
- if (d.size() != 1)
+ if (bit.wire == NULL)
continue;
- bit = d;
- clk = cell->getPort("\\CLK");
- clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
- goto replaced_this_bit;
- }
+ for (auto cell : dff_cells)
+ {
+ if (after && forward_merged_dffs.count(cell))
+ continue;
- return false;
- replaced_this_bit:;
- }
+ SigSpec this_clk = cell->getPort("\\CLK");
+ bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
- return true;
-}
+ if (invbits.count(this_clk)) {
+ this_clk = invbits.at(this_clk);
+ this_clk_polarity = !this_clk_polarity;
+ }
-void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
-{
- log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+ if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
+ if (this_clk != clk)
+ continue;
+ if (this_clk_polarity != clk_polarity)
+ continue;
+ }
- RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
- bool clk_polarity = 0;
+ RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
+ sigmap.apply(q_norm);
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
- if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) {
- log("no (compatible) $dff for address input found.\n");
- return;
- }
+ RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
+ if (d.size() != 1)
+ continue;
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
- if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) {
- log("no (compatible) $dff for data input found.\n");
- return;
- }
+ bit = d;
+ clk = this_clk;
+ clk_polarity = this_clk_polarity;
+ candidate_dffs.insert(cell);
+ goto replaced_this_bit;
+ }
- RTLIL::SigSpec sig_en = cell->getPort("\\EN");
- if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) {
- log("no (compatible) $dff for enable input found.\n");
- return;
- }
+ return false;
+ replaced_this_bit:;
+ }
- if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
- cell->setPort("\\CLK", clk);
- cell->setPort("\\ADDR", sig_addr);
- cell->setPort("\\DATA", sig_data);
- cell->setPort("\\EN", sig_en);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- log("merged $dff to cell.\n");
- return;
+ return true;
}
- log("no (compatible) $dff found.\n");
-}
+ void handle_wr_cell(RTLIL::Cell *cell)
+ {
+ log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
-void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
-{
- normalize_sig(module, sig);
- sig.sort_and_unify();
+ RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
+ bool clk_polarity = 0;
+ candidate_dffs.clear();
- std::stringstream sstr;
- sstr << "$memory_dff_disconnected$" << (autoidx++);
+ RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
+ log("no (compatible) $dff for address input found.\n");
+ return;
+ }
- RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
+ RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+ if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
+ log("no (compatible) $dff for data input found.\n");
+ return;
+ }
- for (auto cell : module->cells())
- if (cell->type == "$dff") {
- RTLIL::SigSpec new_q = cell->getPort("\\Q");
- new_q.replace(sig, new_sig);
- cell->setPort("\\Q", new_q);
+ RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+ if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
+ log("no (compatible) $dff for enable input found.\n");
+ return;
}
-}
-void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
-{
- log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+ if (clk != RTLIL::SigSpec(RTLIL::State::Sx))
+ {
+ for (auto cell : candidate_dffs)
+ forward_merged_dffs.insert(cell);
+
+ cell->setPort("\\CLK", clk);
+ cell->setPort("\\ADDR", sig_addr);
+ cell->setPort("\\DATA", sig_data);
+ cell->setPort("\\EN", sig_en);
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+
+ log("merged $dff to cell.\n");
+ return;
+ }
- bool clk_polarity = 0;
+ log("no (compatible) $dff found.\n");
+ }
- RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
- if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) &&
- clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
+ void disconnect_dff(RTLIL::SigSpec sig)
{
- disconnect_dff(module, sig_data);
- cell->setPort("\\CLK", clk_data);
- cell->setPort("\\DATA", sig_data);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
- log("merged data $dff to cell.\n");
- return;
+ sigmap.apply(sig);
+ sig.sort_and_unify();
+
+ std::stringstream sstr;
+ sstr << "$memory_dff_disconnected$" << (autoidx++);
+
+ RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
+
+ for (auto cell : module->cells())
+ if (cell->type == "$dff") {
+ RTLIL::SigSpec new_q = cell->getPort("\\Q");
+ new_q.replace(sig, new_sig);
+ cell->setPort("\\Q", new_q);
+ }
}
- RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
- if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) &&
- clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
+ void handle_rd_cell(RTLIL::Cell *cell)
{
- cell->setPort("\\CLK", clk_addr);
- cell->setPort("\\ADDR", sig_addr);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
- log("merged address $dff to cell.\n");
- return;
- }
+ log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
- log("no (compatible) $dff found.\n");
-}
+ bool clk_polarity = 0;
-void handle_module(RTLIL::Module *module, bool flag_wr_only)
-{
- std::vector<RTLIL::Cell*> dff_cells;
+ RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
+ RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+
+ for (auto bit : sigmap(sig_data))
+ if (sigbit_users_count[bit] > 1)
+ goto skip_ff_after_read_merging;
- for (auto cell : module->cells())
- if (cell->type == "$dff")
- dff_cells.push_back(cell);
+ if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
+ {
+ bool enable_invert = mux_cells_a.count(sig_data) != 0;
+ Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
+ SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
+
+ sig_data = sigmap(mux->getPort("\\Y"));
+ for (auto bit : sig_data)
+ if (sigbit_users_count[bit] > 1)
+ goto skip_ff_after_read_merging;
+
+ if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
+ {
+ disconnect_dff(sig_data);
+ cell->setPort("\\CLK", clk_data);
+ cell->setPort("\\EN", enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
+ cell->setPort("\\DATA", sig_data);
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ log("merged data $dff with rd enable to cell.\n");
+ return;
+ }
+ }
+ else
+ {
+ if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
+ {
+ disconnect_dff(sig_data);
+ cell->setPort("\\CLK", clk_data);
+ cell->setPort("\\EN", State::S1);
+ cell->setPort("\\DATA", sig_data);
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ log("merged data $dff to cell.\n");
+ return;
+ }
+ }
- for (auto cell : module->selected_cells())
- if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
- handle_wr_cell(module, dff_cells, cell);
+ skip_ff_after_read_merging:;
+ RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
+ RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
+ clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
+ {
+ cell->setPort("\\CLK", clk_addr);
+ cell->setPort("\\EN", State::S1);
+ cell->setPort("\\ADDR", sig_addr);
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
+ log("merged address $dff to cell.\n");
+ return;
+ }
+
+ log("no (compatible) $dff found.\n");
+ }
+
+ void run(bool flag_wr_only)
+ {
+ for (auto wire : module->wires()) {
+ if (wire->port_output)
+ for (auto bit : sigmap(wire))
+ sigbit_users_count[bit]++;
+ }
+
+ for (auto cell : module->cells()) {
+ if (cell->type == "$dff")
+ dff_cells.push_back(cell);
+ if (cell->type == "$mux") {
+ mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
+ mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
+ }
+ if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
+ SigSpec sig_a = cell->getPort("\\A");
+ SigSpec sig_y = cell->getPort("\\Y");
+ if (cell->type == "$not")
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+ if (cell->type == "$logic_not")
+ sig_y.extend_u0(1);
+ for (int i = 0; i < GetSize(sig_y); i++)
+ invbits[sig_y[i]] = sig_a[i];
+ }
+ for (auto &conn : cell->connections())
+ if (!cell->known() || cell->input(conn.first))
+ for (auto bit : sigmap(conn.second))
+ sigbit_users_count[bit]++;
+ }
- if (!flag_wr_only)
for (auto cell : module->selected_cells())
- if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
- handle_rd_cell(module, dff_cells, cell);
-}
+ if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ handle_wr_cell(cell);
+
+ if (!flag_wr_only)
+ for (auto cell : module->selected_cells())
+ if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ handle_rd_cell(cell);
+ }
+};
struct MemoryDffPass : public Pass {
MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
@@ -194,7 +275,7 @@ struct MemoryDffPass : public Pass {
log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
log("interface and yields a synchronous memory port.\n");
log("\n");
- log(" -wr_only\n");
+ log(" -nordfff\n");
log(" do not merge registers on read ports\n");
log("\n");
}
@@ -202,11 +283,11 @@ struct MemoryDffPass : public Pass {
{
bool flag_wr_only = false;
- log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+ log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
- if (args[argidx] == "-wr_only") {
+ if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
flag_wr_only = true;
continue;
}
@@ -214,9 +295,11 @@ struct MemoryDffPass : public Pass {
}
extra_args(args, argidx, design);
- for (auto mod : design->selected_modules())
- handle_module(mod, flag_wr_only);
+ for (auto mod : design->selected_modules()) {
+ MemoryDffWorker worker(mod);
+ worker.run(flag_wr_only);
+ }
}
} MemoryDffPass;
-
+
PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 4fb10a989..bffeec857 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -37,7 +37,7 @@ struct MemoryMapWorker
{
std::stringstream sstr;
sstr << "$memory" << name.str() << token1;
-
+
if (i >= 0)
sstr << "[" << i << "]";
@@ -80,13 +80,20 @@ struct MemoryMapWorker
{
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
+
+ int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
+ int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
+
int mem_size = cell->parameters["\\SIZE"].as_int();
int mem_width = cell->parameters["\\WIDTH"].as_int();
int mem_offset = cell->parameters["\\OFFSET"].as_int();
int mem_abits = cell->parameters["\\ABITS"].as_int();
+ SigSpec init_data = cell->getParam("\\INIT");
+ init_data.extend_u0(mem_size*mem_width, true);
+
// delete unused memory cell
- if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
+ if (wr_ports == 0 && rd_ports == 0) {
module->remove(cell);
return;
}
@@ -95,6 +102,8 @@ struct MemoryMapWorker
RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
+ clocks_pol.bits.resize(wr_ports);
+ clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) {
@@ -110,7 +119,7 @@ struct MemoryMapWorker
// FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en
// is not a simple static 1.
- static_cells_map[wr_addr.as_int()] = wr_data;
+ static_cells_map[wr_addr.as_int() - mem_offset] = wr_data;
static_ports.insert(i);
continue;
}
@@ -165,7 +174,10 @@ struct MemoryMapWorker
w_out_name = genid(cell->name, "", i, "$q");
RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
- w_out->start_offset = mem_offset;
+ SigSpec w_init = init_data.extract(i*mem_width, mem_width);
+
+ if (!w_init.is_fully_undef())
+ w_out->attributes["\\init"] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out));
c->setPort("\\Q", data_reg_out.back());
@@ -180,39 +192,51 @@ struct MemoryMapWorker
{
RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
+ if (mem_offset)
+ rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
+
std::vector<RTLIL::SigSpec> rd_signals;
rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
{
+ RTLIL::Cell *dff_cell = nullptr;
+
if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- c->setPort("\\D", rd_addr);
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
+ dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
+ dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
+ dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+ dff_cell->setPort("\\D", rd_addr);
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
- c->setPort("\\Q", RTLIL::SigSpec(w));
+ dff_cell->setPort("\\Q", RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w);
}
else
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- c->setPort("\\Q", rd_signals.back());
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
+ dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
+ dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+ dff_cell->setPort("\\Q", rd_signals.back());
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w));
- c->setPort("\\D", rd_signals.back());
+ dff_cell->setPort("\\D", rd_signals.back());
+ }
+
+ SigBit en_bit = cell->getPort("\\RD_EN").extract(i);
+ if (en_bit != State::S1) {
+ SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
+ dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit);
+ dff_cell->setPort("\\D", new_d);
}
}
@@ -256,6 +280,10 @@ struct MemoryMapWorker
RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
+
+ if (mem_offset)
+ wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
+
RTLIL::Wire *w_seladdr = addr_decode(wr_addr, RTLIL::SigSpec(i, mem_abits));
int wr_offset = 0;
@@ -335,11 +363,11 @@ struct MemoryMapPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
- log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
+ log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto mod : design->selected_modules())
MemoryMapWorker(design, mod);
}
} MemoryMapPass;
-
+
PRIVATE_NAMESPACE_END
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index a2f89f6d9..f298169de 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -43,7 +43,7 @@ struct MemoryShareWorker
CellTypes cone_ct;
std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
- std::map<std::set<std::map<RTLIL::SigBit, bool>>, RTLIL::SigBit> conditions_logic_cache;
+ std::map<pair<std::set<std::map<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;
// -----------------------------------------------------------------
@@ -79,7 +79,7 @@ struct MemoryShareWorker
}
return false;
}
-
+
for (int i = 0; i < int(sig_s.size()); i++)
{
@@ -109,10 +109,12 @@ struct MemoryShareWorker
return false;
}
- RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, int &created_conditions)
+ RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, SigBit olden, int &created_conditions)
{
- if (conditions_logic_cache.count(conditions))
- return conditions_logic_cache.at(conditions);
+ auto key = make_pair(conditions, olden);
+
+ if (conditions_logic_cache.count(key))
+ return conditions_logic_cache.at(key);
RTLIL::SigSpec terms;
for (auto &cond : conditions) {
@@ -125,10 +127,16 @@ struct MemoryShareWorker
created_conditions++;
}
- if (terms.size() > 1)
+ if (olden.wire != nullptr || olden != State::S1)
+ terms.append(olden);
+
+ if (GetSize(terms) == 0)
+ terms = State::S1;
+
+ if (GetSize(terms) > 1)
terms = module->ReduceAnd(NEW_ID, terms);
- return conditions_logic_cache[conditions] = terms;
+ return conditions_logic_cache[key] = terms;
}
void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports)
@@ -137,15 +145,14 @@ struct MemoryShareWorker
std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
std::set<RTLIL::SigBit> non_feedback_nets;
- for (auto wire_it : module->wires_)
- if (wire_it.second->port_output) {
- std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
+ for (auto wire : module->wires())
+ if (wire->port_output) {
+ std::vector<RTLIL::SigBit> bits = sigmap(wire);
non_feedback_nets.insert(bits.begin(), bits.end());
}
- for (auto cell_it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = cell_it.second;
bool ignore_data_port = false;
if (cell->type == "$mux" || cell->type == "$pmux")
@@ -170,7 +177,7 @@ struct MemoryShareWorker
cell->parameters.at("\\MEMID").decode_string() == memid)
ignore_data_port = true;
- for (auto conn : cell_it.second->connections())
+ for (auto conn : cell->connections())
{
if (ignore_data_port && conn.first == "\\DATA")
continue;
@@ -207,7 +214,7 @@ struct MemoryShareWorker
if (non_feedback_nets.count(sig_data[i]))
goto not_pure_feedback_port;
- async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size()));
+ async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size()));
for (int i = 0; i < int(sig_data.size()); i++)
async_rd_bits[sig_addr][i].insert(sig_data[i]);
@@ -237,13 +244,8 @@ struct MemoryShareWorker
std::map<RTLIL::SigBit, bool> state;
std::set<std::map<RTLIL::SigBit, bool>> conditions;
- if (cell_en[i].wire != NULL) {
- state[cell_en[i]] = false;
- conditions.insert(state);
- }
-
find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions);
- cell_en[i] = conditions_to_logic(conditions, created_conditions);
+ cell_en[i] = conditions_to_logic(conditions, cell_en[i], created_conditions);
}
if (created_conditions) {
@@ -489,8 +491,8 @@ struct MemoryShareWorker
if (wr_ports.size() <= 1)
return;
- ezDefaultSAT ez;
- SatGen satgen(&ez, &modwalker.sigmap);
+ ezSatPtr ez;
+ SatGen satgen(ez.get(), &modwalker.sigmap);
// find list of considered ports and port pairs
@@ -553,7 +555,7 @@ struct MemoryShareWorker
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
{
RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
- port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
+ port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
std::vector<RTLIL::SigBit> bits = sig;
bits_queue.insert(bits.begin(), bits.end());
@@ -582,7 +584,7 @@ struct MemoryShareWorker
vector<int> ez_wire_bits = satgen.importSigSpec(wire);
for (int i : ez_wire_bits)
for (int j : ez_wire_bits)
- if (i != j) ez.assume(ez.NOT(i), j);
+ if (i != j) ez->assume(ez->NOT(i), j);
}
log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
@@ -590,7 +592,7 @@ struct MemoryShareWorker
for (auto cell : sat_cells)
satgen.importCell(cell);
- log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez.numCnfVariables(), ez.numCnfClauses());
+ log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
// merge subsequent ports if possible
@@ -599,13 +601,13 @@ struct MemoryShareWorker
if (!considered_port_pairs.count(i))
continue;
- if (ez.solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
+ if (ez->solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i);
continue;
}
log(" Merging port %d into port %d.\n", i-1, i);
- port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
+ port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR");
RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA");
@@ -663,10 +665,8 @@ struct MemoryShareWorker
std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
sigmap_xmux = sigmap;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
- RTLIL::Cell *cell = it.second;
-
if (cell->type == "$memrd")
memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
@@ -743,11 +743,11 @@ struct MemorySharePass : public Pass {
log("\n");
log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
- log("optimizations) such as opt_share.\n");
+ log("optimizations) such as \"share\" and \"opt_merge\".\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
- log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
+ log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())
MemoryShareWorker(design, module);
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index e650facb4..a0fc31b5e 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -57,6 +57,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
+ cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1));
cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
}
@@ -76,6 +77,41 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
}
+ Const initval = memory->parameters.at("\\INIT");
+ RTLIL::Cell *last_init_cell = nullptr;
+ SigSpec last_init_data;
+ int last_init_addr=0;
+
+ for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
+ Const val = initval.extract(i, mem->width, State::Sx);
+ for (auto bit : val.bits)
+ if (bit != State::Sx)
+ goto found_non_undef_initval;
+ continue;
+ found_non_undef_initval:
+ if (last_init_cell && last_init_addr+1 == i/mem->width) {
+ last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1;
+ last_init_data.append(val);
+ last_init_addr++;
+ } else {
+ if (last_init_cell)
+ last_init_cell->setPort("\\DATA", last_init_data);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
+ cell->parameters["\\MEMID"] = mem_name.str();
+ cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
+ cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
+ cell->parameters["\\WORDS"] = 1;
+ cell->parameters["\\PRIORITY"] = i/mem->width;
+ cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
+ last_init_cell = cell;
+ last_init_addr = i/mem->width;
+ last_init_data = val;
+ }
+ }
+
+ if (last_init_cell)
+ last_init_cell->setPort("\\DATA", last_init_data);
+
module->remove(memory);
}
@@ -102,12 +138,12 @@ struct MemoryUnpackPass : public Pass {
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
- log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
+ log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
} MemoryUnpackPass;
-
+
PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-11 06:09:26 +0000