1 files changed, 10 insertions, 10 deletions

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 649ad83a6..e36e4419d 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -416,7 +416,7 @@ int get_onehot_bit_index(RTLIL::SigSpec signal)
 	return bit_index;
 }
 
-void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv)
+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
 {
 	if (!design->selected(module))
 		return;
@@ -465,7 +465,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 #define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
 #define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
 
-		if (clkinv)
+		if (!noclkinv)
 		{
 			if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
 				handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
@@ -604,7 +604,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				if (cell->type.in(ID($xnor), ID($_XNOR_))) {
 					cover("opt.opt_expr.const_xnor");
 					// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
-					int width = cell->getParam(ID::Y_WIDTH).as_int();
+					int width = GetSize(cell->getPort(ID::Y));
 					replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width));
 					goto next_cell;
 				}
@@ -2064,8 +2064,8 @@ struct OptExprPass : public Pass {
 		log("    -undriven\n");
 		log("        replace undriven nets with undef (x) constants\n");
 		log("\n");
-		log("    -clkinv\n");
-		log("        optimize clock inverters by changing FF types\n");
+		log("    -noclkinv\n");
+		log("        do not optimize clock inverters by changing FF types\n");
 		log("\n");
 		log("    -fine\n");
 		log("        perform fine-grain optimizations\n");
@@ -2085,7 +2085,7 @@ struct OptExprPass : public Pass {
 		bool mux_undef = false;
 		bool mux_bool = false;
 		bool undriven = false;
-		bool clkinv = false;
+		bool noclkinv = false;
 		bool do_fine = false;
 		bool keepdc = false;
 
@@ -2106,8 +2106,8 @@ struct OptExprPass : public Pass {
 				undriven = true;
 				continue;
 			}
-			if (args[argidx] == "-clkinv") {
-				clkinv = true;
+			if (args[argidx] == "-noclkinv") {
+				noclkinv = true;
 				continue;
 			}
 			if (args[argidx] == "-fine") {
@@ -2144,12 +2144,12 @@ struct OptExprPass : public Pass {
 			do {
 				do {
 					did_something = false;
-					replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv);
+					replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
 					if (did_something)
 						design->scratchpad_set_bool("opt.did_something", true);
 				} while (did_something);
 				if (!keepdc)
-					replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv);
+					replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
 				if (did_something)
 					design->scratchpad_set_bool("opt.did_something", true);
 			} while (did_something);