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-rw-r--r--passes/opt/opt_reduce.cc119
1 files changed, 60 insertions, 59 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 8126f3c0d..f74655d1c 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -43,14 +43,14 @@ struct OptReduceWorker
return;
cells.erase(cell);
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
sig_a.sort_and_unify();
pool<RTLIL::SigBit> new_sig_a_bits;
- for (auto &bit : sig_a.to_sigbit_set())
+ for (auto &bit : sig_a)
{
if (bit == RTLIL::State::S0) {
- if (cell->type == "$reduce_and") {
+ if (cell->type == ID($reduce_and)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S0);
break;
@@ -58,7 +58,7 @@ struct OptReduceWorker
continue;
}
if (bit == RTLIL::State::S1) {
- if (cell->type == "$reduce_or") {
+ if (cell->type == ID($reduce_or)) {
new_sig_a_bits.clear();
new_sig_a_bits.insert(RTLIL::State::S1);
break;
@@ -74,8 +74,8 @@ struct OptReduceWorker
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
- if (child_cell->getPort("\\Y")[0] == bit) {
- pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_pool();
+ if (child_cell->getPort(ID::Y)[0] == bit) {
+ pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
@@ -89,22 +89,22 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
- if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
+ if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
total_count++;
}
- cell->setPort("\\A", new_sig_a);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
+ cell->setPort(ID::A, new_sig_a);
+ cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_mux(RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
@@ -125,15 +125,15 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
- RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
- reduce_or_cell->setPort("\\A", this_s);
- reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
- reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
+ reduce_or_cell->setPort(ID::A, this_s);
+ reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
+ reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
+ reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
- reduce_or_cell->setPort("\\Y", this_s);
+ reduce_or_cell->setPort(ID::Y, this_s);
}
new_sig_b.append(this_b);
@@ -149,28 +149,28 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
- module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
- assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
+ module->connect(RTLIL::SigSig(cell->getPort(ID::Y), cell->getPort(ID::A)));
+ assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
module->remove(cell);
}
else
{
- cell->setPort("\\B", new_sig_b);
- cell->setPort("\\S", new_sig_s);
+ cell->setPort(ID::B, new_sig_b);
+ cell->setPort(ID(S), new_sig_s);
if (new_sig_s.size() > 1) {
- cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
+ cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
} else {
- cell->type = "$mux";
- cell->parameters.erase("\\S_WIDTH");
+ cell->type = ID($mux);
+ cell->parameters.erase(ID(S_WIDTH));
}
}
}
void opt_mux_bits(RTLIL::Cell *cell)
{
- std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID::A)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID::B)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID::Y)).to_sigbit_vector();
std::vector<RTLIL::SigBit> new_sig_y;
RTLIL::SigSig old_sig_conn;
@@ -211,33 +211,32 @@ struct OptReduceWorker
if (new_sig_y.size() != sig_y.size())
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
- log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
- log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
+ log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
+ log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
- cell->setPort("\\A", RTLIL::SigSpec());
+ cell->setPort(ID::A, RTLIL::SigSpec());
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_a = cell->getPort("\\A");
+ RTLIL::SigSpec new_a = cell->getPort(ID::A);
new_a.append(in_tuple.at(0));
- cell->setPort("\\A", new_a);
+ cell->setPort(ID::A, new_a);
}
- cell->setPort("\\B", RTLIL::SigSpec());
- for (int i = 1; i <= cell->getPort("\\S").size(); i++)
+ cell->setPort(ID::B, RTLIL::SigSpec());
+ for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_b = cell->getPort("\\B");
+ RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.append(in_tuple.at(i));
- cell->setPort("\\B", new_b);
+ cell->setPort(ID::B, new_b);
}
- cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
- cell->setPort("\\Y", new_sig_y);
+ cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
+ cell->setPort(ID::Y, new_sig_y);
- log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
- log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
+ log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
+ log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
module->connect(old_sig_conn);
- module->check();
did_something = true;
total_count++;
@@ -255,15 +254,15 @@ struct OptReduceWorker
SigPool mem_wren_sigs;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$mem")
- mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
- if (cell->type == "$memwr")
- mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
+ if (cell->type == ID($mem))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
+ if (cell->type == ID($memwr))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
- mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
+ if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
}
bool keep_expanding_mem_wren_sigs = true;
@@ -271,12 +270,12 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
- if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
- !mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
+ if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
+ if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) ||
+ !mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B))))
keep_expanding_mem_wren_sigs = true;
- mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
- mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::A)));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::B)));
}
}
}
@@ -288,7 +287,7 @@ struct OptReduceWorker
// merge trees of reduce_* cells to one single cell and unify input vectors
// (only handle reduce_and and reduce_or for various reasons)
- const char *type_list[] = { "$reduce_or", "$reduce_and" };
+ const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
for (auto type : type_list)
{
SigSet<RTLIL::Cell*> drivers;
@@ -298,7 +297,7 @@ struct OptReduceWorker
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
- drivers.insert(assign_map(cell->getPort("\\Y")), cell);
+ drivers.insert(assign_map(cell->getPort(ID::Y)), cell);
cells.insert(cell);
}
@@ -313,25 +312,27 @@ struct OptReduceWorker
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells_)
- if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
+ if ((it.second->type == ID($mux) || it.second->type == ID($pmux)) && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
{
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
- if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
+ if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y))))
opt_mux_bits(cell);
opt_mux(cell);
}
}
+
+ module->check();
}
};
struct OptReducePass : public Pass {
OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -352,7 +353,7 @@ struct OptReducePass : public Pass {
log(" alias for -fine\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
bool do_fine = false;
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-23 08:35:34 +0000