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-rw-r--r--passes/opt/opt_reduce.cc80
1 files changed, 40 insertions, 40 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 8aadd1f23..80ec89744 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -42,7 +42,7 @@ struct OptReduceWorker
return;
cells.erase(cell);
- RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
std::set<RTLIL::SigBit> new_sig_a_bits;
for (auto &bit : sig_a.to_sigbit_set())
@@ -72,8 +72,8 @@ struct OptReduceWorker
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
- if (child_cell->get("\\Y")[0] == bit) {
- std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set();
+ if (child_cell->getPort("\\Y")[0] == bit) {
+ std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_set();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
@@ -86,23 +86,23 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
- if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) {
+ if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;
OPT_DID_SOMETHING = true;
total_count++;
}
- cell->set("\\A", new_sig_a);
+ cell->setPort("\\A", new_sig_a);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_mux(RTLIL::Cell *cell)
{
- RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
- RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
- RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
RTLIL::SigSpec new_sig_b, new_sig_s;
std::set<RTLIL::SigSpec> handled_sig;
@@ -124,14 +124,14 @@ struct OptReduceWorker
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
- reduce_or_cell->set("\\A", this_s);
+ reduce_or_cell->setPort("\\A", this_s);
reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
- reduce_or_cell->set("\\Y", this_s);
+ reduce_or_cell->setPort("\\Y", this_s);
}
new_sig_b.append(this_b);
@@ -148,14 +148,14 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
- module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A")));
- assign_map.add(cell->get("\\Y"), cell->get("\\A"));
+ module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
+ assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
module->remove(cell);
}
else
{
- cell->set("\\B", new_sig_b);
- cell->set("\\S", new_sig_s);
+ cell->setPort("\\B", new_sig_b);
+ cell->setPort("\\S", new_sig_s);
if (new_sig_s.size() > 1) {
cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
} else {
@@ -167,9 +167,9 @@ struct OptReduceWorker
void opt_mux_bits(RTLIL::Cell *cell)
{
- std::vector<RTLIL::SigBit> sig_a = assign_map(cell->get("\\A")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_b = assign_map(cell->get("\\B")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
std::vector<RTLIL::SigBit> new_sig_y;
RTLIL::SigSig old_sig_conn;
@@ -210,29 +210,29 @@ struct OptReduceWorker
if (new_sig_y.size() != sig_y.size())
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
- log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
- log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
+ log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
+ log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
- cell->set("\\A", RTLIL::SigSpec());
+ cell->setPort("\\A", RTLIL::SigSpec());
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_a = cell->get("\\A");
+ RTLIL::SigSpec new_a = cell->getPort("\\A");
new_a.append(in_tuple.at(0));
- cell->set("\\A", new_a);
+ cell->setPort("\\A", new_a);
}
- cell->set("\\B", RTLIL::SigSpec());
- for (int i = 1; i <= cell->get("\\S").size(); i++)
+ cell->setPort("\\B", RTLIL::SigSpec());
+ for (int i = 1; i <= cell->getPort("\\S").size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
- RTLIL::SigSpec new_b = cell->get("\\B");
+ RTLIL::SigSpec new_b = cell->getPort("\\B");
new_b.append(in_tuple.at(i));
- cell->set("\\B", new_b);
+ cell->setPort("\\B", new_b);
}
cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
- cell->set("\\Y", new_sig_y);
+ cell->setPort("\\Y", new_sig_y);
- log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
- log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
+ log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
+ log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
module->connect(old_sig_conn);
@@ -256,14 +256,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mem")
- mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
+ mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
if (cell->type == "$memwr")
- mem_wren_sigs.add(assign_map(cell->get("\\EN")));
+ mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
- mem_wren_sigs.add(assign_map(cell->get("\\D")));
+ if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
+ mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
}
bool keep_expanding_mem_wren_sigs = true;
@@ -271,12 +271,12 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
- if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
- !mem_wren_sigs.check_all(assign_map(cell->get("\\B"))))
+ if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
+ if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
+ !mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
keep_expanding_mem_wren_sigs = true;
- mem_wren_sigs.add(assign_map(cell->get("\\A")));
- mem_wren_sigs.add(assign_map(cell->get("\\B")));
+ mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
+ mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
}
}
}
@@ -298,7 +298,7 @@ struct OptReduceWorker
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
- drivers.insert(assign_map(cell->get("\\Y")), cell);
+ drivers.insert(assign_map(cell->getPort("\\Y")), cell);
cells.insert(cell);
}
@@ -320,7 +320,7 @@ struct OptReduceWorker
{
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
- if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y"))))
+ if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
opt_mux_bits(cell);
opt_mux(cell);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 12:57:07 +0000