1 files changed, 73 insertions, 73 deletions

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 1eeca2748..ca0be54d2 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -34,13 +34,13 @@ struct WreduceConfig
 	WreduceConfig()
 	{
 		supported_cell_types = pool<IdString>({
-			"$not", "$pos", "$neg",
-			"$and", "$or", "$xor", "$xnor",
-			"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
-			"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
-			"$add", "$sub", "$mul", // "$div", "$mod", "$pow",
-			"$mux", "$pmux",
-			"$dff", "$adff"
+			ID($not), ID($pos), ID($neg),
+			ID($and), ID($or), ID($xor), ID($xnor),
+			ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
+			ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
+			ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($pow),
+			ID($mux), ID($pmux),
+			ID($dff), ID($adff)
 		});
 	}
 };
@@ -64,10 +64,10 @@ struct WreduceWorker
 	{
 		// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
 
-		SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
-		SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
-		SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
-		SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
+		SigSpec sig_a = mi.sigmap(cell->getPort(ID(A)));
+		SigSpec sig_b = mi.sigmap(cell->getPort(ID(B)));
+		SigSpec sig_s = mi.sigmap(cell->getPort(ID(S)));
+		SigSpec sig_y = mi.sigmap(cell->getPort(ID(Y)));
 		std::vector<SigBit> bits_removed;
 
 		if (sig_y.has_const())
@@ -130,9 +130,9 @@ struct WreduceWorker
 		for (auto bit : new_work_queue_bits)
 			work_queue_bits.insert(bit);
 
-		cell->setPort("\\A", new_sig_a);
-		cell->setPort("\\B", new_sig_b);
-		cell->setPort("\\Y", new_sig_y);
+		cell->setPort(ID(A), new_sig_a);
+		cell->setPort(ID(B), new_sig_b);
+		cell->setPort(ID(Y), new_sig_y);
 		cell->fixup_parameters();
 
 		module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
@@ -142,8 +142,8 @@ struct WreduceWorker
 	{
 		// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
 
-		SigSpec sig_d = mi.sigmap(cell->getPort("\\D"));
-		SigSpec sig_q = mi.sigmap(cell->getPort("\\Q"));
+		SigSpec sig_d = mi.sigmap(cell->getPort(ID(D)));
+		SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q)));
 		Const initval;
 
 		int width_before = GetSize(sig_q);
@@ -214,14 +214,14 @@ struct WreduceWorker
 			work_queue_bits.insert(bit);
 
 		// Narrow ARST_VALUE parameter to new size.
-		if (cell->parameters.count("\\ARST_VALUE")) {
-			Const arst_value = cell->getParam("\\ARST_VALUE");
+		if (cell->parameters.count(ID(ARST_VALUE))) {
+			Const arst_value = cell->getParam(ID(ARST_VALUE));
 			arst_value.bits.resize(GetSize(sig_q));
-			cell->setParam("\\ARST_VALUE", arst_value);
+			cell->setParam(ID(ARST_VALUE), arst_value);
 		}
 
-		cell->setPort("\\D", sig_d);
-		cell->setPort("\\Q", sig_q);
+		cell->setPort(ID(D), sig_d);
+		cell->setPort(ID(Q), sig_q);
 		cell->fixup_parameters();
 	}
 
@@ -230,7 +230,7 @@ struct WreduceWorker
 		port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
 		SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
 
-		if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
+		if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr)))
 			port_signed = false;
 
 		int bits_removed = 0;
@@ -264,13 +264,13 @@ struct WreduceWorker
 		if (!cell->type.in(config->supported_cell_types))
 			return;
 
-		if (cell->type.in("$mux", "$pmux"))
+		if (cell->type.in(ID($mux), ID($pmux)))
 			return run_cell_mux(cell);
 
-		if (cell->type.in("$dff", "$adff"))
+		if (cell->type.in(ID($dff), ID($adff)))
 			return run_cell_dff(cell);
 
-		SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
+		SigSpec sig = mi.sigmap(cell->getPort(ID(Y)));
 
 		if (sig.has_const())
 			return;
@@ -278,10 +278,10 @@ struct WreduceWorker
 
 		// Reduce size of ports A and B based on constant input bits and size of output port
 
-		int max_port_a_size = cell->hasPort("\\A") ? GetSize(cell->getPort("\\A")) : -1;
-		int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
+		int max_port_a_size = cell->hasPort(ID(A)) ? GetSize(cell->getPort(ID(A))) : -1;
+		int max_port_b_size = cell->hasPort(ID(B)) ? GetSize(cell->getPort(ID(B))) : -1;
 
-		if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
+		if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
 			max_port_a_size = min(max_port_a_size, GetSize(sig));
 			max_port_b_size = min(max_port_b_size, GetSize(sig));
 		}
@@ -289,32 +289,32 @@ struct WreduceWorker
 		bool port_a_signed = false;
 		bool port_b_signed = false;
 
-		if (max_port_a_size >= 0 && cell->type != "$shiftx")
+		if (max_port_a_size >= 0 && cell->type != ID($shiftx))
 			run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
 
 		if (max_port_b_size >= 0)
 			run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
 
-		if (cell->hasPort("\\A") && cell->hasPort("\\B") && port_a_signed && port_b_signed) {
-			SigSpec sig_a = mi.sigmap(cell->getPort("\\A")), sig_b = mi.sigmap(cell->getPort("\\B"));
+		if (cell->hasPort(ID(A)) && cell->hasPort(ID(B)) && port_a_signed && port_b_signed) {
+			SigSpec sig_a = mi.sigmap(cell->getPort(ID(A))), sig_b = mi.sigmap(cell->getPort(ID(B)));
 			if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
 					GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
 				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
 						log_id(module), log_id(cell), log_id(cell->type));
-				cell->setParam("\\A_SIGNED", 0);
-				cell->setParam("\\B_SIGNED", 0);
+				cell->setParam(ID(A_SIGNED), 0);
+				cell->setParam(ID(B_SIGNED), 0);
 				port_a_signed = false;
 				port_b_signed = false;
 				did_something = true;
 			}
 		}
 
-		if (cell->hasPort("\\A") && !cell->hasPort("\\B") && port_a_signed) {
-			SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
+		if (cell->hasPort(ID(A)) && !cell->hasPort(ID(B)) && port_a_signed) {
+			SigSpec sig_a = mi.sigmap(cell->getPort(ID(A)));
 			if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
 				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
 						log_id(module), log_id(cell), log_id(cell->type));
-				cell->setParam("\\A_SIGNED", 0);
+				cell->setParam(ID(A_SIGNED), 0);
 				port_a_signed = false;
 				did_something = true;
 			}
@@ -324,7 +324,7 @@ struct WreduceWorker
 		// Reduce size of port Y based on sizes for A and B and unused bits in Y
 
 		int bits_removed = 0;
-		if (port_a_signed && cell->type == "$shr") {
+		if (port_a_signed && cell->type == ID($shr)) {
 			// do not reduce size of output on $shr cells with signed A inputs
 		} else {
 			while (GetSize(sig) > 0)
@@ -342,20 +342,20 @@ struct WreduceWorker
 			}
 		}
 
-		if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub"))
+		if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
 		{
-			bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub";
+			bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub);
 
 			int a_size = 0, b_size = 0;
-			if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
-			if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B"));
+			if (cell->hasPort(ID(A))) a_size = GetSize(cell->getPort(ID(A)));
+			if (cell->hasPort(ID(B))) b_size = GetSize(cell->getPort(ID(B)));
 
 			int max_y_size = max(a_size, b_size);
 
-			if (cell->type.in("$add", "$sub"))
+			if (cell->type.in(ID($add), ID($sub)))
 				max_y_size++;
 
-			if (cell->type == "$mul")
+			if (cell->type == ID($mul))
 				max_y_size = a_size + b_size;
 
 			while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
@@ -374,7 +374,7 @@ struct WreduceWorker
 		if (bits_removed) {
 			log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
 					bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
-			cell->setPort("\\Y", sig);
+			cell->setPort(ID(Y), sig);
 			did_something = true;
 		}
 
@@ -387,8 +387,8 @@ struct WreduceWorker
 	static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
 	{
 		int count = w->attributes.size();
-		count -= w->attributes.count("\\src");
-		count -= w->attributes.count("\\unused_bits");
+		count -= w->attributes.count(ID(src));
+		count -= w->attributes.count(ID(unused_bits));
 		return count;
 	}
 
@@ -398,11 +398,11 @@ struct WreduceWorker
 		SigMap init_attr_sigmap = mi.sigmap;
 
 		for (auto w : module->wires()) {
-			if (w->get_bool_attribute("\\keep"))
+			if (w->get_bool_attribute(ID(keep)))
 				for (auto bit : mi.sigmap(w))
 					keep_bits.insert(bit);
-			if (w->attributes.count("\\init")) {
-				Const initval = w->attributes.at("\\init");
+			if (w->attributes.count(ID(init))) {
+				Const initval = w->attributes.at(ID(init));
 				SigSpec initsig = init_attr_sigmap(w);
 				int width = std::min(GetSize(initval), GetSize(initsig));
 				for (int i = 0; i < width; i++)
@@ -459,8 +459,8 @@ struct WreduceWorker
 
 		if (!remove_init_bits.empty()) {
 			for (auto w : module->wires()) {
-				if (w->attributes.count("\\init")) {
-					Const initval = w->attributes.at("\\init");
+				if (w->attributes.count(ID(init))) {
+					Const initval = w->attributes.at(ID(init));
 					Const new_initval(State::Sx, GetSize(w));
 					SigSpec initsig = init_attr_sigmap(w);
 					int width = std::min(GetSize(initval), GetSize(initsig));
@@ -468,7 +468,7 @@ struct WreduceWorker
 						if (!remove_init_bits.count(initsig[i]))
 							new_initval[i] = initval[i];
 					}
-					w->attributes.at("\\init") = new_initval;
+					w->attributes.at(ID(init)) = new_initval;
 				}
 			}
 		}
@@ -528,23 +528,23 @@ struct WreducePass : public Pass {
 
 			for (auto c : module->selected_cells())
 			{
-				if (c->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
-						"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
-						"$logic_not", "$logic_and", "$logic_or") && GetSize(c->getPort("\\Y")) > 1) {
-					SigSpec sig = c->getPort("\\Y");
+				if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
+						ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
+						ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID(Y))) > 1) {
+					SigSpec sig = c->getPort(ID(Y));
 					if (!sig.has_const()) {
-						c->setPort("\\Y", sig[0]);
-						c->setParam("\\Y_WIDTH", 1);
+						c->setPort(ID(Y), sig[0]);
+						c->setParam(ID(Y_WIDTH), 1);
 						sig.remove(0);
 						module->connect(sig, Const(0, GetSize(sig)));
 					}
 				}
 
-				if (c->type.in("$div", "$mod", "$pow"))
+				if (c->type.in(ID($div), ID($mod), ID($pow)))
 				{
-					SigSpec A = c->getPort("\\A");
+					SigSpec A = c->getPort(ID(A));
 					int original_a_width = GetSize(A);
-					if (c->getParam("\\A_SIGNED").as_bool()) {
+					if (c->getParam(ID(A_SIGNED)).as_bool()) {
 						while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
 							A.remove(GetSize(A)-1, 1);
 					} else {
@@ -554,13 +554,13 @@ struct WreducePass : public Pass {
 					if (original_a_width != GetSize(A)) {
 						log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
 								original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
-						c->setPort("\\A", A);
-						c->setParam("\\A_WIDTH", GetSize(A));
+						c->setPort(ID(A), A);
+						c->setParam(ID(A_WIDTH), GetSize(A));
 					}
 
-					SigSpec B = c->getPort("\\B");
+					SigSpec B = c->getPort(ID(B));
 					int original_b_width = GetSize(B);
-					if (c->getParam("\\B_SIGNED").as_bool()) {
+					if (c->getParam(ID(B_SIGNED)).as_bool()) {
 						while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
 							B.remove(GetSize(B)-1, 1);
 					} else {
@@ -570,24 +570,24 @@ struct WreducePass : public Pass {
 					if (original_b_width != GetSize(B)) {
 						log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
 								original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
-						c->setPort("\\B", B);
-						c->setParam("\\B_WIDTH", GetSize(B));
+						c->setPort(ID(B), B);
+						c->setParam(ID(B_WIDTH), GetSize(B));
 					}
 				}
 
-				if (!opt_memx && c->type.in("$memrd", "$memwr", "$meminit")) {
-					IdString memid = c->getParam("\\MEMID").decode_string();
+				if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
+					IdString memid = c->getParam(ID(MEMID)).decode_string();
 					RTLIL::Memory *mem = module->memories.at(memid);
 					if (mem->start_offset >= 0) {
-						int cur_addrbits = c->getParam("\\ABITS").as_int();
+						int cur_addrbits = c->getParam(ID(ABITS)).as_int();
 						int max_addrbits = ceil_log2(mem->start_offset + mem->size);
 						if (cur_addrbits > max_addrbits) {
 							log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
 									cur_addrbits-max_addrbits, cur_addrbits,
-									c->type == "$memrd" ? "read" : c->type == "$memwr" ? "write" : "init",
+									c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
 									log_id(module), log_id(c), log_id(memid));
-							c->setParam("\\ABITS", max_addrbits);
-							c->setPort("\\ADDR", c->getPort("\\ADDR").extract(0, max_addrbits));
+							c->setParam(ID(ABITS), max_addrbits);
+							c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits));
 						}
 					}
 				}