diff options
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 | ||||
| -rw-r--r-- | passes/opt/opt_mem.cc | 143 | ||||
| -rw-r--r-- | passes/opt/opt_share.cc | 15 |
4 files changed, 156 insertions, 5 deletions
diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index eb07e9452..002c1a6a1 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -1,6 +1,7 @@ OBJS += passes/opt/opt.o OBJS += passes/opt/opt_merge.o +OBJS += passes/opt/opt_mem.o OBJS += passes/opt/opt_muxtree.o OBJS += passes/opt/opt_reduce.o OBJS += passes/opt/opt_rmdff.o diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 6cf66fb95..4a2f170b8 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -978,7 +978,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), - log_id(module), "$eq" ? "$logic_not" : "$reduce_bool"); + log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool"); cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { cell->setPort(ID::A, cell->getPort(ID::B)); diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc new file mode 100644 index 000000000..98d3551eb --- /dev/null +++ b/passes/opt/opt_mem.cc @@ -0,0 +1,143 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct OptMemWorker +{ + RTLIL::Design *design; + RTLIL::Module *module; + SigMap sigmap; + bool restart; + + dict<IdString, vector<IdString>> memrd, memwr, meminit; + pool<IdString> remove_mem, remove_cells; + + OptMemWorker(RTLIL::Module *module) : design(module->design), module(module), sigmap(module), restart(false) + { + for (auto &it : module->memories) + { + memrd[it.first]; + memwr[it.first]; + meminit[it.first]; + } + + for (auto cell : module->cells()) + { + if (cell->type == ID($memrd)) { + IdString id = cell->getParam(ID(MEMID)).decode_string(); + memrd.at(id).push_back(cell->name); + } + + if (cell->type == ID($memwr)) { + IdString id = cell->getParam(ID(MEMID)).decode_string(); + memwr.at(id).push_back(cell->name); + } + + if (cell->type == ID($meminit)) { + IdString id = cell->getParam(ID(MEMID)).decode_string(); + meminit.at(id).push_back(cell->name); + } + } + } + + ~OptMemWorker() + { + for (auto it : remove_mem) + { + for (auto cell_name : memrd[it]) + module->remove(module->cell(cell_name)); + for (auto cell_name : memwr[it]) + module->remove(module->cell(cell_name)); + for (auto cell_name : meminit[it]) + module->remove(module->cell(cell_name)); + + delete module->memories.at(it); + module->memories.erase(it); + } + + for (auto cell_name : remove_cells) + module->remove(module->cell(cell_name)); + } + + int run(RTLIL::Memory *mem) + { + if (restart || remove_mem.count(mem->name)) + return 0; + + if (memwr.at(mem->name).empty() && meminit.at(mem->name).empty()) { + log("Removing memory %s.%s with no write ports or init data.\n", log_id(module), log_id(mem)); + remove_mem.insert(mem->name); + return 1; + } + + return 0; + } +}; + +struct OptMemPass : public Pass { + OptMemPass() : Pass("opt_mem", "optimize memories") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" opt_mem [options] [selection]\n"); + log("\n"); + log("This pass performs various optimizations on memories in the design.\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing OPT_MEM pass (optimize memories).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + // if (args[argidx] == "-nomux") { + // mode_nomux = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + int total_count = 0; + for (auto module : design->selected_modules()) { + while (1) { + int cnt = 0; + OptMemWorker worker(module); + for (auto &it : module->memories) + if (module->selected(it.second)) + cnt += worker.run(it.second); + if (!cnt && !worker.restart) + break; + total_count += cnt; + } + } + + if (total_count) + design->scratchpad_set_bool("opt.did_something", true); + log("Performed a total of %d transformations.\n", total_count); + } +} OptMemPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 2c456705c..f59f978a6 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -83,7 +83,9 @@ struct ExtSigSpec { bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; } }; -#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor) +#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_) + +#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor) #define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand) @@ -250,14 +252,19 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< shared_op->setPort(ID(CO), alu_co.extract(0, conn_width)); } - shared_op->setParam(ID(Y_WIDTH), conn_width); + bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); + + if (!is_fine) + shared_op->setParam(ID(Y_WIDTH), conn_width); if (decode_port(shared_op, ID::A, &assign_map) == operand) { shared_op->setPort(ID::B, mux_to_oper); - shared_op->setParam(ID(B_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(B_WIDTH), max_width); } else { shared_op->setPort(ID::A, mux_to_oper); - shared_op->setParam(ID(A_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(A_WIDTH), max_width); } } |