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-rw-r--r--passes/opt/muxpack.cc14
-rw-r--r--passes/opt/opt_clean.cc44
-rw-r--r--passes/opt/opt_expr.cc392
-rw-r--r--passes/opt/opt_lut.cc22
-rw-r--r--passes/opt/opt_lut_ins.cc26
-rw-r--r--passes/opt/opt_mem.cc6
-rw-r--r--passes/opt/opt_merge.cc246
-rw-r--r--passes/opt/opt_muxtree.cc12
-rw-r--r--passes/opt/opt_reduce.cc36
-rw-r--r--passes/opt/opt_rmdff.cc178
-rw-r--r--passes/opt/opt_share.cc32
-rw-r--r--passes/opt/pmux2shiftx.cc38
-rw-r--r--passes/opt/share.cc214
-rw-r--r--passes/opt/wreduce.cc60
14 files changed, 687 insertions, 633 deletions
diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index c40c02acd..9df49ab3c 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -208,8 +208,8 @@ struct MuxpackWorker
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
- SigSpec s_sig = sigmap(cell->getPort(ID(S)));
- s_sig.append(sigmap(prev_cell->getPort(ID(S))));
+ SigSpec s_sig = sigmap(cell->getPort(ID::S));
+ s_sig.append(sigmap(prev_cell->getPort(ID::S)));
if (!excl_db.query(s_sig))
goto start_cell;
}
@@ -271,26 +271,26 @@ struct MuxpackWorker
first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B);
- SigSpec s_sig = first_cell->getPort(ID(S));
+ SigSpec s_sig = first_cell->getPort(ID::S);
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
- s_sig.append(cursor_cell->getPort(ID(S)));
+ s_sig.append(cursor_cell->getPort(ID::S));
}
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
- s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID(S))));
+ s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
}
remove_cells.insert(cursor_cell);
}
first_cell->setPort(ID::B, b_sig);
- first_cell->setPort(ID(S), s_sig);
- first_cell->setParam(ID(S_WIDTH), GetSize(s_sig));
+ first_cell->setPort(ID::S, s_sig);
+ first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
cursor += cases;
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index cac265a52..da3961218 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -183,8 +183,8 @@ void rmunused_module_cells(Module *module, bool verbose)
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count(ID(src));
- count -= w->attributes.count(ID(unused_bits));
+ count -= w->attributes.count(ID::src);
+ count -= w->attributes.count(ID::unused_bits);
return count;
}
@@ -203,8 +203,8 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
return !(w2->port_input && w2->port_output);
if (w1->name[0] == '\\' && w2->name[0] == '\\') {
- if (regs.check_any(s1) != regs.check_any(s2))
- return regs.check_any(s2);
+ if (regs.check(s1) != regs.check(s2))
+ return regs.check(s2);
if (direct_wires.count(w1) != direct_wires.count(w2))
return direct_wires.count(w2) != 0;
if (conns.check_any(s1) != conns.check_any(s2))
@@ -317,12 +317,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
log_assert(GetSize(s1) == GetSize(s2));
Const initval;
- if (wire->attributes.count(ID(init)))
- initval = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init))
+ initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports
@@ -358,14 +358,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
s2[i] = initval[i];
initval[i] = State::Sx;
}
- new_conn.first.append_bit(s1[i]);
- new_conn.second.append_bit(s2[i]);
+ new_conn.first.append(s1[i]);
+ new_conn.second.append(s2[i]);
}
if (new_conn.first.size() > 0) {
if (initval.is_fully_undef())
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at(ID(init)) = initval;
+ wire->attributes.at(ID::init) = initval;
used_signals.add(new_conn.first);
used_signals.add(new_conn.second);
module->connect(new_conn);
@@ -383,11 +383,11 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
}
}
if (unused_bits.empty() || wire->port_id != 0)
- wire->attributes.erase(ID(unused_bits));
+ wire->attributes.erase(ID::unused_bits);
else
- wire->attributes[ID(unused_bits)] = RTLIL::Const(unused_bits);
+ wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits);
} else {
- wire->attributes.erase(ID(unused_bits));
+ wire->attributes.erase(ID::unused_bits);
}
}
}
@@ -419,18 +419,18 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
dict<SigBit, State> qbits;
for (auto cell : module->cells())
- if (fftypes.cell_known(cell->type) && cell->hasPort(ID(Q)))
+ if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
{
- SigSpec sig = cell->getPort(ID(Q));
+ SigSpec sig = cell->getPort(ID::Q);
for (int i = 0; i < GetSize(sig); i++)
{
SigBit bit = sig[i];
- if (bit.wire == nullptr || bit.wire->attributes.count(ID(init)) == 0)
+ if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
continue;
- Const init = bit.wire->attributes.at(ID(init));
+ Const init = bit.wire->attributes.at(ID::init);
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue;
@@ -445,10 +445,10 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
if (!purge_mode && wire->name[0] == '\\')
continue;
- if (wire->attributes.count(ID(init)) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
- Const init = wire->attributes.at(ID(init));
+ Const init = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{
@@ -471,7 +471,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
did_something = true;
next_wire:;
}
@@ -487,7 +487,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
- bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed);
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 4a2f170b8..1a4dd9239 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN
bool did_something;
-void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
+void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
- CellTypes ct(design);
SigMap sigmap(module);
SigPool driven_signals;
SigPool used_signals;
@@ -51,9 +50,9 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
}
for (auto wire : module->wires()) {
- if (wire->attributes.count(ID(init))) {
+ if (wire->attributes.count(ID::init)) {
SigSpec sig = sigmap(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[sig[i]] = make_pair(wire, initval[i]);
@@ -99,18 +98,18 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
for (auto wire : revisit_initwires) {
SigSpec sig = sm2(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval[i] = State::Sx;
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
did_something = true;
- } else if (initval != wire->attributes.at(ID(init))) {
+ } else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
- wire->attributes[ID(init)] = initval;
+ wire->attributes[ID::init] = initval;
did_something = true;
}
}
@@ -137,7 +136,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
{
IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A;
- bool a_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
+ bool a_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool();
RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID::A));
@@ -193,11 +192,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
for (auto &it : grouped_bits[i]) {
for (auto &bit : it.second) {
- new_conn.first.append_bit(bit);
- new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size()));
+ new_conn.first.append(bit);
+ new_conn.second.append(RTLIL::SigBit(new_y, new_a.size()));
}
- new_a.append_bit(it.first.first);
- new_b.append_bit(it.first.second);
+ new_a.append(it.first.first);
+ new_b.append(it.first.second);
}
if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) {
@@ -210,17 +209,17 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort(ID::A, new_a);
- c->parameters[ID(A_WIDTH)] = new_a.size();
- c->parameters[ID(A_SIGNED)] = false;
+ c->parameters[ID::A_WIDTH] = new_a.size();
+ c->parameters[ID::A_SIGNED] = false;
if (b_name == ID::B) {
c->setPort(ID::B, new_b);
- c->parameters[ID(B_WIDTH)] = new_b.size();
- c->parameters[ID(B_SIGNED)] = false;
+ c->parameters[ID::B_WIDTH] = new_b.size();
+ c->parameters[ID::B_SIGNED] = false;
}
c->setPort(ID::Y, new_y);
- c->parameters[ID(Y_WIDTH)] = new_y->width;
+ c->parameters[ID::Y_WIDTH] = new_y->width;
c->check();
module->connect(new_conn);
@@ -373,7 +372,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
- invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID(S)));
+ invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
if (ct_combinational.cell_known(cell->type))
for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = assign_map(conn.second);
@@ -402,36 +401,36 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (clkinv)
{
if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
- handle_polarity_inv(cell, ID(CLK), ID(CLK_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
- handle_polarity_inv(cell, ID(SET), ID(SET_POLARITY), assign_map, invert_map);
- handle_polarity_inv(cell, ID(CLR), ID(CLR_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
+ handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
}
if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
- handle_polarity_inv(cell, ID(EN), ID(EN_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID(C), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID(E), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID(E), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID(E), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
}
bool detect_const_and = false;
@@ -440,13 +439,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($reduce_and), ID($_AND_)))
detect_const_and = true;
- if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
+ if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_and = true;
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
detect_const_or = true;
- if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
+ if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_or = true;
if (detect_const_and || detect_const_or)
@@ -496,6 +495,42 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
+ if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
+ {
+ SigBit sig_a = assign_map(cell->getPort(ID::A));
+ SigBit sig_b = assign_map(cell->getPort(ID::B));
+ if (!sig_a.wire)
+ std::swap(sig_a, sig_b);
+ if (sig_b == State::S0 || sig_b == State::S1) {
+ if (cell->type.in(ID($xor), ID($_XOR_))) {
+ cover("opt.opt_expr.xor_buffer");
+ SigSpec sig_y;
+ if (cell->type == ID($xor))
+ sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
+ else if (cell->type == ID($_XOR_))
+ sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
+ else log_abort();
+ replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
+ goto next_cell;
+ }
+ if (cell->type.in(ID($xnor), ID($_XNOR_))) {
+ cover("opt.opt_expr.xnor_buffer");
+ SigSpec sig_y;
+ if (cell->type == ID($xnor)) {
+ sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
+ int width = cell->getParam(ID::Y_WIDTH).as_int();
+ sig_y.append(RTLIL::Const(State::S1, width-1));
+ }
+ else if (cell->type == ID($_XNOR_))
+ sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
+ else log_abort();
+ replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
+ goto next_cell;
+ }
+ log_abort();
+ }
+ }
+
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
{
@@ -536,7 +571,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a);
- cell->parameters.at(ID(A_WIDTH)) = GetSize(new_sig_a);
+ cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true;
}
}
@@ -559,7 +594,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b);
- cell->parameters.at(ID(B_WIDTH)) = GetSize(new_sig_b);
+ cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true;
}
}
@@ -585,7 +620,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
- cell->parameters.at(ID(A_WIDTH)) = 1;
+ cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
}
}
@@ -611,7 +646,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
- cell->parameters.at(ID(A_WIDTH)) = 1;
+ cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
}
}
@@ -637,7 +672,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b);
- cell->parameters.at(ID(B_WIDTH)) = 1;
+ cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true;
}
}
@@ -651,10 +686,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
int i;
for (i = 0; i < GetSize(sig_y); i++) {
- if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
- module->connect(sig_y[i], sig_a[i]);
- else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
- module->connect(sig_y[i], sig_b[i]);
+ RTLIL::SigBit b = sig_b.at(i, State::Sx);
+ RTLIL::SigBit a = sig_a.at(i, State::Sx);
+ if (b == State::S0 && a != State::Sx)
+ module->connect(sig_y[i], a);
+ else if (sub && b == State::S1 && a == State::S1)
+ module->connect(sig_y[i], State::S0);
+ else if (!sub && a == State::S0 && b != State::Sx)
+ module->connect(sig_y[i], b);
else
break;
}
@@ -668,18 +707,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
}
- if (cell->type == "$alu")
+ if (cell->type == ID($alu))
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
- RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
- RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
- RTLIL::SigSpec sig_x = cell->getPort(ID(X));
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
-
- if (sig_ci.wire || sig_bi.wire)
- goto next_cell;
+ RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
@@ -690,14 +726,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
int i;
for (i = 0; i < GetSize(sig_y); i++) {
- if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
- module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
+ RTLIL::SigBit b = sig_b.at(i, State::Sx);
+ RTLIL::SigBit a = sig_a.at(i, State::Sx);
+ if (b == State::S0 && a != State::Sx) {
module->connect(sig_y[i], sig_a[i]);
+ module->connect(sig_x[i], sub ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_co[i], sub ? State::S1 : State::S0);
}
- else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
- module->connect(sig_x[i], sig_b[i]);
- module->connect(sig_y[i], sig_b[i]);
+ else if (sub && b == State::S1 && a == State::S1) {
+ module->connect(sig_y[i], State::S0);
+ module->connect(sig_x[i], module->Not(NEW_ID, a));
+ module->connect(sig_co[i], State::S0);
+ }
+ else if (!sub && a == State::S0 && b != State::Sx) {
+ module->connect(sig_y[i], b);
+ module->connect(sig_x[i], b);
module->connect(sig_co[i], State::S0);
}
else
@@ -707,9 +750,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.fine.$alu");
cell->setPort(ID::A, sig_a.extract_end(i));
cell->setPort(ID::B, sig_b.extract_end(i));
- cell->setPort(ID(X), sig_x.extract_end(i));
+ cell->setPort(ID::X, sig_x.extract_end(i));
cell->setPort(ID::Y, sig_y.extract_end(i));
- cell->setPort(ID(CO), sig_co.extract_end(i));
+ cell->setPort(ID::CO, sig_co.extract_end(i));
cell->fixup_parameters();
did_something = true;
}
@@ -761,7 +804,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
- cell->setParam(ID(A_WIDTH), width);
+ cell->setParam(ID::A_WIDTH, width);
did_something = true;
goto next_cell;
}
@@ -774,13 +817,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell;
}
- if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID(S)))) != 0) {
+ if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
- cell->setPort(ID(S), invert_map.at(assign_map(cell->getPort(ID(S)))));
+ cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S))));
did_something = true;
goto next_cell;
}
@@ -842,13 +885,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (input.match("11")) ACTION_DO_Y(0);
if (input.match(" *")) ACTION_DO_Y(x);
if (input.match("* ")) ACTION_DO_Y(x);
- if (input.match(" 0")) ACTION_DO(ID::Y, input.extract(1, 1));
- if (input.match("0 ")) ACTION_DO(ID::Y, input.extract(0, 1));
}
if (cell->type == ID($_MUX_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort(ID(S)));
+ input.append(cell->getPort(ID::S));
input.append(cell->getPort(ID::B));
input.append(cell->getPort(ID::A));
assign_map.apply(input);
@@ -862,7 +903,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type = ID($_NOT_);
cell->setPort(ID::A, input.extract(0, 1));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
goto next_cell;
}
if (input.match("11 ")) ACTION_DO_Y(1);
@@ -878,7 +919,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
- RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID(E) : ID(EN));
+ RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID::E : ID::EN);
RTLIL::SigSpec a = cell->getPort(ID::A);
assign_map.apply(input);
assign_map.apply(a);
@@ -899,10 +940,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
- if (cell->parameters[ID(A_WIDTH)].as_int() != cell->parameters[ID(B_WIDTH)].as_int()) {
- int width = max(cell->parameters[ID(A_WIDTH)].as_int(), cell->parameters[ID(B_WIDTH)].as_int());
- a.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
- b.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
+ if (cell->parameters[ID::A_WIDTH].as_int() != cell->parameters[ID::B_WIDTH].as_int()) {
+ int width = max(cell->parameters[ID::A_WIDTH].as_int(), cell->parameters[ID::B_WIDTH].as_int());
+ a.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
+ b.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
}
RTLIL::SigSpec new_a, new_b;
@@ -912,7 +953,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
- new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
+ new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
goto next_cell;
}
@@ -925,7 +966,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (new_a.size() == 0) {
cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
- new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
+ new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "empty", ID::Y, new_y);
goto next_cell;
}
@@ -934,13 +975,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
- cell->parameters[ID(A_WIDTH)] = new_a.size();
- cell->parameters[ID(B_WIDTH)] = new_b.size();
+ cell->parameters[ID::A_WIDTH] = new_a.size();
+ cell->parameters[ID::B_WIDTH] = new_b.size();
}
}
- if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID(Y_WIDTH)].as_int() == 1 &&
- cell->parameters[ID(A_WIDTH)].as_int() == 1 && cell->parameters[ID(B_WIDTH)].as_int() == 1)
+ if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
+ cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1)
{
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
@@ -964,8 +1005,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->type = ID($not);
- cell->parameters.erase(ID(B_WIDTH));
- cell->parameters.erase(ID(B_SIGNED));
+ cell->parameters.erase(ID::B_WIDTH);
+ cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B);
did_something = true;
}
@@ -982,29 +1023,29 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
- cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
+ cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
+ cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
}
cell->unsetPort(ID::B);
- cell->unsetParam(ID(B_SIGNED));
- cell->unsetParam(ID(B_WIDTH));
+ cell->unsetParam(ID::B_SIGNED);
+ cell->unsetParam(ID::B_WIDTH);
did_something = true;
goto next_cell;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const())
{
- bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID(A_SIGNED)).as_bool();
- int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID(B_SIGNED)).as_bool());
+ bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
+ int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool());
if (cell->type.in(ID($shl), ID($sshl)))
shift_bits *= -1;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
- RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID(Y_WIDTH)).as_int());
+ RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
if (GetSize(sig_a) < GetSize(sig_y))
- sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID(A_SIGNED)).as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits;
@@ -1032,12 +1073,26 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
bool identity_wrt_b = false;
bool arith_inverse = false;
- if (cell->type.in(ID($add), ID($sub), ID($or), ID($xor)))
+ if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor)))
{
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
- if (cell->type != ID($sub) && a.is_fully_const() && a.as_bool() == false)
+ bool sub = cell->type == ID($sub);
+
+ if (cell->type == ID($alu)) {
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
+
+ sub = (sig_ci == State::S1 && sig_bi == State::S1);
+
+ // If not a subtraction, yet there is a carry or B is inverted
+ // then no optimisation is possible as carry will not be constant
+ if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
+ goto next_cell;
+ }
+
+ if (!sub && a.is_fully_const() && a.as_bool() == false)
identity_wrt_b = true;
if (b.is_fully_const() && b.as_bool() == false)
@@ -1057,10 +1112,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
- if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID(A_SIGNED)).as_bool(), arith_inverse))
+ if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID::A_SIGNED).as_bool(), arith_inverse))
identity_wrt_b = true;
else
- if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID(B_SIGNED)).as_bool(), arith_inverse))
+ if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID::B_SIGNED).as_bool(), arith_inverse))
identity_wrt_a = true;
}
@@ -1075,23 +1130,33 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (identity_wrt_a || identity_wrt_b)
{
if (identity_wrt_a)
- cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
+ cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
if (identity_wrt_b)
- cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
+ cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
+ if (cell->type == ID($alu)) {
+ int y_width = GetSize(cell->getPort(ID::Y));
+ module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width));
+ module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
+ cell->unsetPort(ID::BI);
+ cell->unsetPort(ID::CI);
+ cell->unsetPort(ID::X);
+ cell->unsetPort(ID::CO);
+ }
+
if (!identity_wrt_a) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
- cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
+ cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
+ cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
}
cell->type = arith_inverse ? ID($neg) : ID($pos);
cell->unsetPort(ID::B);
- cell->parameters.erase(ID(B_WIDTH));
- cell->parameters.erase(ID(B_SIGNED));
+ cell->parameters.erase(ID::B_WIDTH);
+ cell->parameters.erase(ID::B_SIGNED);
cell->check();
did_something = true;
@@ -1102,7 +1167,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID(S)));
+ replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S));
goto next_cell;
}
@@ -1110,15 +1175,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::A, cell->getPort(ID(S)));
+ cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($not);
} else
cell->type = ID($_NOT_);
@@ -1129,16 +1194,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::A, cell->getPort(ID(S)));
- cell->unsetPort(ID(S));
+ cell->setPort(ID::A, cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(B_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters[ID(B_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::B_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters[ID::B_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($and);
} else
cell->type = ID($_AND_);
@@ -1149,16 +1214,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::B, cell->getPort(ID(S)));
- cell->unsetPort(ID(S));
+ cell->setPort(ID::B, cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(B_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters[ID(B_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::B_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters[ID::B_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($or);
} else
cell->type = ID($_OR_);
@@ -1170,14 +1235,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec new_a, new_b, new_s;
int width = GetSize(cell->getPort(ID::A));
if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
- cell->getPort(ID(S)).is_fully_undef()) {
+ cell->getPort(ID::S).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
goto next_cell;
}
- for (int i = 0; i < cell->getPort(ID(S)).size(); i++) {
+ for (int i = 0; i < cell->getPort(ID::S).size(); i++) {
RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width);
- RTLIL::SigSpec old_s = cell->getPort(ID(S)).extract(i, 1);
+ RTLIL::SigSpec old_s = cell->getPort(ID::S).extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef())
continue;
new_b.append(old_b);
@@ -1199,48 +1264,48 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s);
goto next_cell;
}
- if (cell->getPort(ID(S)).size() != new_s.size()) {
+ if (cell->getPort(ID::S).size() != new_s.size()) {
cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
- GetSize(cell->getPort(ID(S))) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
+ GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
- cell->setPort(ID(S), new_s);
+ cell->setPort(ID::S, new_s);
if (new_s.size() > 1) {
cell->type = ID($pmux);
- cell->parameters[ID(S_WIDTH)] = new_s.size();
+ cell->parameters[ID::S_WIDTH] = new_s.size();
} else {
cell->type = ID($mux);
- cell->parameters.erase(ID(S_WIDTH));
+ cell->parameters.erase(ID::S_WIDTH);
}
did_something = true;
}
}
#define FOLD_1ARG_CELL(_t) \
- if (cell->type == "$" #_t) { \
+ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \
assign_map.apply(a); \
if (a.is_fully_const()) { \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
- cell->parameters[ID(A_SIGNED)].as_bool(), false, \
- cell->parameters[ID(Y_WIDTH)].as_int())); \
+ cell->parameters[ID::A_SIGNED].as_bool(), false, \
+ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \
goto next_cell; \
} \
}
#define FOLD_2ARG_CELL(_t) \
- if (cell->type == "$" #_t) { \
+ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \
RTLIL::SigSpec b = cell->getPort(ID::B); \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
- cell->parameters[ID(A_SIGNED)].as_bool(), \
- cell->parameters[ID(B_SIGNED)].as_bool(), \
- cell->parameters[ID(Y_WIDTH)].as_int())); \
+ cell->parameters[ID::A_SIGNED].as_bool(), \
+ cell->parameters[ID::B_SIGNED].as_bool(), \
+ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
goto next_cell; \
@@ -1289,7 +1354,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
// be very conservative with optimizing $mux cells as we do not want to break mux trees
if (cell->type == ID($mux)) {
- RTLIL::SigSpec input = assign_map(cell->getPort(ID(S)));
+ RTLIL::SigSpec input = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B));
if (input.is_fully_const())
@@ -1300,8 +1365,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!keepdc && cell->type == ID($mul))
{
- bool a_signed = cell->parameters[ID(A_SIGNED)].as_bool();
- bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
+ bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
+ bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
bool swapped_ab = false;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
@@ -1342,8 +1407,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!swapped_ab) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
- cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
+ cell->parameters.at(ID::A_WIDTH) = cell->parameters.at(ID::B_WIDTH);
+ cell->parameters.at(ID::A_SIGNED) = cell->parameters.at(ID::B_SIGNED);
}
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
@@ -1352,8 +1417,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.pop_back();
cell->type = ID($shl);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
- cell->parameters[ID(B_SIGNED)] = false;
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
+ cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
cell->check();
@@ -1365,7 +1430,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!keepdc && cell->type.in(ID($div), ID($mod)))
{
- bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
+ bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
SigSpec sig_b = assign_map(cell->getPort(ID::B));
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
@@ -1403,8 +1468,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.pop_back();
cell->type = ID($shr);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
- cell->parameters[ID(B_SIGNED)] = false;
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
+ cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
cell->check();
}
@@ -1421,7 +1486,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.push_back(State::S0);
cell->type = ID($and);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->setPort(ID::B, new_b);
cell->check();
}
@@ -1442,10 +1507,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
contradiction_cache.promote(State::S0);
contradiction_cache.promote(State::S1);
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width);
SigSpec sig_a = cell->getPort(ID::A);
@@ -1499,8 +1564,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
- cell->setParam(ID(A_WIDTH), GetSize(sig_a));
- cell->setParam(ID(B_WIDTH), GetSize(sig_b));
+ cell->setParam(ID::A_WIDTH, GetSize(sig_a));
+ cell->setParam(ID::B_WIDTH, GetSize(sig_b));
did_something = true;
goto next_cell;
@@ -1513,9 +1578,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
IdString cmp_type = cell->type;
SigSpec var_sig = cell->getPort(ID::A);
SigSpec const_sig = cell->getPort(ID::B);
- int var_width = cell->parameters[ID(A_WIDTH)].as_int();
- int const_width = cell->parameters[ID(B_WIDTH)].as_int();
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ int var_width = cell->parameters[ID::A_WIDTH].as_int();
+ int const_width = cell->parameters[ID::B_WIDTH].as_int();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
if (!const_sig.is_fully_const())
{
@@ -1590,7 +1655,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
int const_bit_set = get_highest_hot_index(const_sig);
- if(const_bit_set >= var_width)
+ if (const_bit_set >= var_width)
{
string cmp_name;
if (cmp_type == ID($lt) || cmp_type == ID($le))
@@ -1737,13 +1802,14 @@ struct OptExprPass : public Pass {
}
extra_args(args, argidx, design);
+ CellTypes ct(design);
for (auto module : design->selected_modules())
{
log("Optimizing module %s.\n", log_id(module));
if (undriven) {
did_something = false;
- replace_undriven(design, module);
+ replace_undriven(module, ct);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
}
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index c4f278706..12927d052 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -41,8 +41,8 @@ struct OptLutWorker
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
SigSpec lut_input = sigmap(lut->getPort(ID::A));
- int lut_width = lut->getParam(ID(WIDTH)).as_int();
- Const lut_table = lut->getParam(ID(LUT));
+ int lut_width = lut->getParam(ID::WIDTH).as_int();
+ Const lut_table = lut->getParam(ID::LUT);
int lut_index = 0;
for (int i = 0; i < lut_width; i++)
@@ -107,7 +107,7 @@ struct OptLutWorker
if (lut_output.wire->get_bool_attribute(ID::keep))
continue;
- int lut_width = cell->getParam(ID(WIDTH)).as_int();
+ int lut_width = cell->getParam(ID::WIDTH).as_int();
SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0;
@@ -305,7 +305,7 @@ struct OptLutWorker
auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
- int lutA_width = lutA->getParam(ID(WIDTH)).as_int();
+ int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
@@ -323,7 +323,7 @@ struct OptLutWorker
auto lutB = port.cell;
SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
- int lutB_width = lutB->getParam(ID(WIDTH)).as_int();
+ int lutB_width = lutB->getParam(ID::WIDTH).as_int();
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
@@ -372,7 +372,7 @@ struct OptLutWorker
log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
else if (lutB_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
- else if (lutB->get_bool_attribute(ID(lut_keep)))
+ else if (lutB->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_A;
@@ -380,7 +380,7 @@ struct OptLutWorker
log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
else if (lutA_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
- else if (lutA->get_bool_attribute(ID(lut_keep)))
+ else if (lutA->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_B;
@@ -440,7 +440,7 @@ struct OptLutWorker
lutR_unique.insert(bit);
}
- int lutM_width = lutM->getParam(ID(WIDTH)).as_int();
+ int lutM_width = lutM->getParam(ID::WIDTH).as_int();
SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++)
@@ -482,11 +482,11 @@ struct OptLutWorker
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
- log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID(LUT)).as_string().c_str());
- log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID(LUT)).as_string().c_str());
+ log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
+ log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
- lutM->setParam(ID(LUT), lutM_new_table);
+ lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs);
lutM->setPort(ID::Y, lutB_output);
diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc
index cf5248ced..1d32e84bb 100644
--- a/passes/opt/opt_lut_ins.cc
+++ b/passes/opt/opt_lut_ins.cc
@@ -80,7 +80,7 @@ struct OptLutInsPass : public Pass {
continue;
inputs = cell->getPort(ID::A).bits();
output = cell->getPort(ID::Y);
- lut = cell->getParam(ID(LUT));
+ lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin") {
if (cell->type == ID(LUT1)) {
inputs = {
@@ -125,20 +125,20 @@ struct OptLutInsPass : public Pass {
// Not a LUT.
continue;
}
- lut = cell->getParam(ID(INIT));
+ lut = cell->getParam(ID::INIT);
if (techname == "xilinx")
- output = cell->getPort(ID(O));
+ output = cell->getPort(ID::O);
else
- output = cell->getPort(ID(F));
+ output = cell->getPort(ID::F);
} else if (techname == "ecp5") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
cell->getPort(ID::B),
- cell->getPort(ID(C)),
- cell->getPort(ID(D)),
+ cell->getPort(ID::C),
+ cell->getPort(ID::D),
};
- lut = cell->getParam(ID(INIT));
+ lut = cell->getParam(ID::INIT);
output = cell->getPort(ID(Z));
ignore_const = true;
} else {
@@ -217,19 +217,19 @@ struct OptLutInsPass : public Pass {
module->connect(output, new_lut[0]);
} else {
if (techname == "") {
- cell->setParam(ID(LUT), new_lut);
- cell->setParam(ID(WIDTH), GetSize(new_inputs));
+ cell->setParam(ID::LUT, new_lut);
+ cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs);
} else if (techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4);
- cell->setParam(ID(INIT), new_lut);
+ cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]);
cell->setPort(ID::B, new_inputs[1]);
- cell->setPort(ID(C), new_inputs[2]);
- cell->setPort(ID(D), new_inputs[3]);
+ cell->setPort(ID::C, new_inputs[2]);
+ cell->setPort(ID::D, new_inputs[3]);
} else {
// xilinx, gowin
- cell->setParam(ID(INIT), new_lut);
+ cell->setParam(ID::INIT, new_lut);
if (techname == "xilinx")
log_assert(GetSize(new_inputs) <= 6);
else
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
index 98d3551eb..ff9c06453 100644
--- a/passes/opt/opt_mem.cc
+++ b/passes/opt/opt_mem.cc
@@ -45,17 +45,17 @@ struct OptMemWorker
for (auto cell : module->cells())
{
if (cell->type == ID($memrd)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
memrd.at(id).push_back(cell->name);
}
if (cell->type == ID($memwr)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
memwr.at(id).push_back(cell->name);
}
if (cell->type == ID($meminit)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
meminit.at(id).push_back(cell->name);
}
}
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 8823a9061..a861bd7a4 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -26,7 +26,6 @@
#include <stdio.h>
#include <set>
-#define USE_CELL_HASH_CACHE
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@@ -41,13 +40,11 @@ struct OptMergeWorker
CellTypes ct;
int total_count;
-#ifdef USE_CELL_HASH_CACHE
- dict<const RTLIL::Cell*, std::string> cell_hash_cache;
-#endif
+ SHA1 checksum;
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
- SigSpec sig_s = conn.at(ID(S));
+ SigSpec sig_s = conn.at(ID::S);
SigSpec sig_b = conn.at(ID::B);
int s_width = GetSize(sig_s);
@@ -59,16 +56,15 @@ struct OptMergeWorker
std::sort(sb_pairs.begin(), sb_pairs.end());
- conn[ID(S)] = SigSpec();
+ conn[ID::S] = SigSpec();
conn[ID::B] = SigSpec();
for (auto &it : sb_pairs) {
- conn[ID(S)].append(it.first);
+ conn[ID::S].append(it.first);
conn[ID::B].append(it.second);
}
}
-#ifdef USE_CELL_HASH_CACHE
std::string int_to_hash_string(unsigned int v)
{
if (v == 0)
@@ -83,14 +79,9 @@ struct OptMergeWorker
std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
{
- if (cell_hash_cache.count(cell) > 0)
- return cell_hash_cache[cell];
-
+ vector<string> hash_conn_strings;
std::string hash_string = cell->type.str() + "\n";
- for (auto &it : cell->parameters)
- hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
-
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
@@ -119,18 +110,27 @@ struct OptMergeWorker
alt_conn = *conn;
assign_map.apply(alt_conn.at(ID::A));
assign_map.apply(alt_conn.at(ID::B));
- assign_map.apply(alt_conn.at(ID(S)));
+ assign_map.apply(alt_conn.at(ID::S));
sort_pmux_conn(alt_conn);
conn = &alt_conn;
}
- vector<string> hash_conn_strings;
-
for (auto &it : *conn) {
- if (cell->output(it.first))
- continue;
- RTLIL::SigSpec sig = it.second;
- assign_map.apply(sig);
+ RTLIL::SigSpec sig;
+ if (cell->output(it.first)) {
+ if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ // For the 'Q' output of state elements,
+ // use its (* init *) attribute value
+ for (const auto &b : dff_init_map(it.second))
+ sig.append(b.wire ? State::Sx : b);
+ }
+ else
+ continue;
+ }
+ else
+ sig = assign_map(it.second);
string s = "C " + it.first.str() + "=";
for (auto &chunk : sig.chunks()) {
if (chunk.wire)
@@ -143,50 +143,59 @@ struct OptMergeWorker
hash_conn_strings.push_back(s + "\n");
}
+ for (auto &it : cell->parameters)
+ hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
+
std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
for (auto it : hash_conn_strings)
hash_string += it;
- cell_hash_cache[cell] = sha1(hash_string);
- return cell_hash_cache[cell];
+ checksum.update(hash_string);
+ return checksum.final();
}
-#endif
- bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool &lt)
+ bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
{
-#ifdef USE_CELL_HASH_CACHE
- std::string hash1 = hash_cell_parameters_and_connections(cell1);
- std::string hash2 = hash_cell_parameters_and_connections(cell2);
-
- if (hash1 != hash2) {
- lt = hash1 < hash2;
- return true;
- }
-#endif
-
- if (cell1->parameters != cell2->parameters) {
- std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
- std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
- lt = p1 < p2;
- return true;
- }
-
- dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
- dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
-
- for (auto &it : conn1) {
- if (cell1->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
- }
-
- for (auto &it : conn2) {
- if (cell2->output(it.first))
- it.second = RTLIL::SigSpec();
- else
- assign_map.apply(it.second);
+ log_assert(cell1 != cell2);
+ if (cell1->type != cell2->type) return false;
+
+ if (cell1->parameters != cell2->parameters)
+ return false;
+
+ if (cell1->connections_.size() != cell2->connections_.size())
+ return false;
+ for (const auto &it : cell1->connections_)
+ if (!cell2->connections_.count(it.first))
+ return false;
+
+ decltype(Cell::connections_) conn1, conn2;
+ conn1.reserve(cell1->connections_.size());
+ conn2.reserve(cell1->connections_.size());
+
+ for (const auto &it : cell1->connections_) {
+ if (cell1->output(it.first)) {
+ if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+ cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
+ cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ // For the 'Q' output of state elements,
+ // use the (* init *) attribute value
+ auto &sig1 = conn1[it.first];
+ for (const auto &b : dff_init_map(it.second))
+ sig1.append(b.wire ? State::Sx : b);
+ auto &sig2 = conn2[it.first];
+ for (const auto &b : dff_init_map(cell2->getPort(it.first)))
+ sig2.append(b.wire ? State::Sx : b);
+ }
+ else {
+ conn1[it.first] = RTLIL::SigSpec();
+ conn2[it.first] = RTLIL::SigSpec();
+ }
+ }
+ else {
+ conn1[it.first] = assign_map(it.second);
+ conn2[it.first] = assign_map(cell2->getPort(it.first));
+ }
}
if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
@@ -215,54 +224,9 @@ struct OptMergeWorker
sort_pmux_conn(conn2);
}
- if (conn1 != conn2) {
- std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
- std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
- lt = c1 < c2;
- return true;
- }
-
- if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
- cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
- cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
- std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
- for (size_t i = 0; i < q1.size(); i++)
- if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
- lt = q1.at(i) < q2.at(i);
- return true;
- }
- }
-
- return false;
+ return conn1 == conn2;
}
- bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
- {
- if (cell1->type != cell2->type)
- return cell1->type < cell2->type;
-
- if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
- return cell1 < cell2;
-
- if (cell1->has_keep_attr() || cell2->has_keep_attr())
- return cell1 < cell2;
-
- bool lt;
- if (compare_cell_parameters_and_connections(cell1, cell2, lt))
- return lt;
-
- return false;
- }
-
- struct CompareCells {
- OptMergeWorker *that;
- CompareCells(OptMergeWorker *that) : that(that) {}
- bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
- return that->compare_cells(cell1, cell2);
- }
- };
-
OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
{
@@ -289,8 +253,8 @@ struct OptMergeWorker
dff_init_map.set(module);
for (auto &it : module->wires_)
- if (it.second->attributes.count(ID(init)) != 0) {
- Const initval = it.second->attributes.at(ID(init));
+ if (it.second->attributes.count(ID::init) != 0) {
+ Const initval = it.second->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]);
@@ -299,9 +263,6 @@ struct OptMergeWorker
bool did_something = true;
while (did_something)
{
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.clear();
-#endif
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size());
for (auto &it : module->cells_) {
@@ -312,42 +273,51 @@ struct OptMergeWorker
}
did_something = false;
- std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
+ dict<std::string, RTLIL::Cell*> sharemap;
for (auto cell : cells)
{
- if (sharemap.count(cell) > 0) {
- did_something = true;
- log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
- for (auto &it : cell->connections()) {
- if (cell->output(it.first)) {
- RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
- log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
- log_signal(it.second), log_signal(other_sig));
- module->connect(RTLIL::SigSig(it.second, other_sig));
- assign_map.add(it.second, other_sig);
-
- if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
- cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
- for (auto c : it.second.chunks()) {
- auto jt = c.wire->attributes.find(ID(init));
- if (jt == c.wire->attributes.end())
- continue;
- for (int i = c.offset; i < c.offset + c.width; i++)
- jt->second[i] = State::Sx;
+ if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
+ continue;
+
+ auto hash = hash_cell_parameters_and_connections(cell);
+ auto r = sharemap.insert(std::make_pair(hash, cell));
+ if (!r.second) {
+ if (compare_cell_parameters_and_connections(cell, r.first->second)) {
+ if (cell->has_keep_attr()) {
+ if (r.first->second->has_keep_attr())
+ continue;
+ std::swap(r.first->second, cell);
+ }
+
+
+ did_something = true;
+ log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
+ for (auto &it : cell->connections()) {
+ if (cell->output(it.first)) {
+ RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
+ log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
+ log_signal(it.second), log_signal(other_sig));
+ module->connect(RTLIL::SigSig(it.second, other_sig));
+ assign_map.add(it.second, other_sig);
+
+ if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
+ cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ for (auto c : it.second.chunks()) {
+ auto jt = c.wire->attributes.find(ID::init);
+ if (jt == c.wire->attributes.end())
+ continue;
+ for (int i = c.offset; i < c.offset + c.width; i++)
+ jt->second[i] = State::Sx;
+ }
+ dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
- dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
}
+ log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+ module->remove(cell);
+ total_count++;
}
- log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
-#ifdef USE_CELL_HASH_CACHE
- cell_hash_cache.erase(cell);
-#endif
- module->remove(cell);
- total_count++;
- } else {
- sharemap[cell] = cell;
}
}
}
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 3c486bbcc..d076addae 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -88,7 +88,7 @@ struct OptMuxtreeWorker
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
- RTLIL::SigSpec sig_s = cell->getPort(ID(S));
+ RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
muxinfo_t muxinfo;
@@ -229,7 +229,7 @@ struct OptMuxtreeWorker
RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B);
- RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S));
+ RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y);
RTLIL::SigSpec sig_ports = sig_b;
@@ -257,12 +257,12 @@ struct OptMuxtreeWorker
mi.cell->setPort(ID::A, new_sig_a);
mi.cell->setPort(ID::B, new_sig_b);
- mi.cell->setPort(ID(S), new_sig_s);
+ mi.cell->setPort(ID::S, new_sig_s);
if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux);
- mi.cell->parameters.erase(ID(S_WIDTH));
+ mi.cell->parameters.erase(ID::S_WIDTH);
} else {
- mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s));
+ mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s));
}
}
}
@@ -366,7 +366,7 @@ struct OptMuxtreeWorker
idict<int> ctrl_bits;
if (portname == ID::B)
width = GetSize(muxinfo.cell->getPort(ID::A));
- for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false))
+ for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false))
ctrl_bits(bit);
int port_idx = 0, port_off = 0;
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index f74655d1c..f640f50a0 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -96,7 +96,7 @@ struct OptReduceWorker
}
cell->setPort(ID::A, new_sig_a);
- cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return;
}
@@ -104,7 +104,7 @@ struct OptReduceWorker
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
@@ -127,9 +127,9 @@ struct OptReduceWorker
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
- reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
- reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
- reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
+ reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
+ reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
@@ -156,12 +156,12 @@ struct OptReduceWorker
else
{
cell->setPort(ID::B, new_sig_b);
- cell->setPort(ID(S), new_sig_s);
+ cell->setPort(ID::S, new_sig_s);
if (new_sig_s.size() > 1) {
- cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
+ cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
cell->type = ID($mux);
- cell->parameters.erase(ID(S_WIDTH));
+ cell->parameters.erase(ID::S_WIDTH);
}
}
}
@@ -192,13 +192,13 @@ struct OptReduceWorker
if (all_tuple_bits_same)
{
- old_sig_conn.first.append_bit(sig_y.at(i));
- old_sig_conn.second.append_bit(sig_a.at(i));
+ old_sig_conn.first.append(sig_y.at(i));
+ old_sig_conn.second.append(sig_a.at(i));
}
else if (consolidated_in_tuples_map.count(in_tuple))
{
- old_sig_conn.first.append_bit(sig_y.at(i));
- old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
+ old_sig_conn.first.append(sig_y.at(i));
+ old_sig_conn.second.append(consolidated_in_tuples_map.at(in_tuple));
}
else
{
@@ -222,14 +222,14 @@ struct OptReduceWorker
}
cell->setPort(ID::B, RTLIL::SigSpec());
- for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
+ for (int i = 1; i <= cell->getPort(ID::S).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.append(in_tuple.at(i));
cell->setPort(ID::B, new_b);
}
- cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size());
cell->setPort(ID::Y, new_sig_y);
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
@@ -255,14 +255,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mem))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
if (cell->type == ID($memwr))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
+ if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
}
bool keep_expanding_mem_wren_sigs = true;
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 0bf74098a..81326a417 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -41,7 +41,7 @@ void remove_init_attr(SigSpec sig)
for (auto bit : assign_map(sig))
if (init_attributes.count(bit))
for (auto wbit : init_attributes.at(bit))
- wbit.wire->attributes.at(ID(init))[wbit.offset] = State::Sx;
+ wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx;
}
bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
@@ -49,17 +49,17 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
SigSpec sig_set, sig_clr;
State pol_set, pol_clr;
- if (cell->hasPort(ID(S)))
- sig_set = cell->getPort(ID(S));
+ if (cell->hasPort(ID::S))
+ sig_set = cell->getPort(ID::S);
- if (cell->hasPort(ID(R)))
- sig_clr = cell->getPort(ID(R));
+ if (cell->hasPort(ID::R))
+ sig_clr = cell->getPort(ID::R);
- if (cell->hasPort(ID(SET)))
- sig_set = cell->getPort(ID(SET));
+ if (cell->hasPort(ID::SET))
+ sig_set = cell->getPort(ID::SET);
- if (cell->hasPort(ID(CLR)))
- sig_clr = cell->getPort(ID(CLR));
+ if (cell->hasPort(ID::CLR))
+ sig_clr = cell->getPort(ID::CLR);
log_assert(GetSize(sig_set) == GetSize(sig_clr));
@@ -72,16 +72,16 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else
if (cell->type.in(ID($dffsr), ID($dlatchsr))) {
- pol_set = cell->parameters[ID(SET_POLARITY)].as_bool() ? State::S1 : State::S0;
- pol_clr = cell->parameters[ID(CLR_POLARITY)].as_bool() ? State::S1 : State::S0;
+ pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0;
+ pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0;
} else
log_abort();
State npol_set = pol_set == State::S0 ? State::S1 : State::S0;
State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0;
- SigSpec sig_d = cell->getPort(ID(D));
- SigSpec sig_q = cell->getPort(ID(Q));
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
bool did_something = false;
bool proper_sr = false;
@@ -139,18 +139,18 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
if (cell->type.in(ID($dffsr), ID($dlatchsr)))
{
- cell->setParam(ID(WIDTH), GetSize(sig_d));
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setParam(ID::WIDTH, GetSize(sig_d));
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
}
else
{
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
}
if (proper_sr)
@@ -171,24 +171,24 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod));
cell->type = ID($adff);
- cell->setParam(ID(ARST_POLARITY), unified_pol);
- cell->setParam(ID(ARST_VALUE), reset_val);
- cell->setPort(ID(ARST), sig_reset);
-
- cell->unsetParam(ID(SET_POLARITY));
- cell->unsetParam(ID(CLR_POLARITY));
- cell->unsetPort(ID(SET));
- cell->unsetPort(ID(CLR));
+ cell->setParam(ID::ARST_POLARITY, unified_pol);
+ cell->setParam(ID::ARST_VALUE, reset_val);
+ cell->setPort(ID::ARST, sig_reset);
+
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
}
else
{
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod));
cell->type = ID($dff);
- cell->unsetParam(ID(SET_POLARITY));
- cell->unsetParam(ID(CLR_POLARITY));
- cell->unsetPort(ID(SET));
- cell->unsetPort(ID(CLR));
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
}
return true;
@@ -208,8 +208,8 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod));
cell->type = new_type;
- cell->unsetPort(ID(S));
- cell->unsetPort(ID(R));
+ cell->unsetPort(ID::S);
+ cell->unsetPort(ID::R);
return true;
}
@@ -223,17 +223,17 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
State on_state, off_state;
if (dlatch->type == ID($dlatch)) {
- sig_e = assign_map(dlatch->getPort(ID(EN)));
- on_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S1 : State::S0;
- off_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S0 : State::S1;
+ sig_e = assign_map(dlatch->getPort(ID::EN));
+ on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0;
+ off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1;
} else
if (dlatch->type == ID($_DLATCH_P_)) {
- sig_e = assign_map(dlatch->getPort(ID(E)));
+ sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S1;
off_state = State::S0;
} else
if (dlatch->type == ID($_DLATCH_N_)) {
- sig_e = assign_map(dlatch->getPort(ID(E)));
+ sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S0;
off_state = State::S1;
} else
@@ -242,15 +242,15 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
if (sig_e == off_state)
{
RTLIL::Const val_init;
- for (auto bit : dff_init_map(dlatch->getPort(ID(Q))))
+ for (auto bit : dff_init_map(dlatch->getPort(ID::Q)))
val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
- mod->connect(dlatch->getPort(ID(Q)), val_init);
+ mod->connect(dlatch->getPort(ID::Q), val_init);
goto delete_dlatch;
}
if (sig_e == on_state)
{
- mod->connect(dlatch->getPort(ID(Q)), dlatch->getPort(ID(D)));
+ mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D));
goto delete_dlatch;
}
@@ -258,7 +258,7 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
delete_dlatch:
log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
- remove_init_attr(dlatch->getPort(ID(Q)));
+ remove_init_attr(dlatch->getPort(ID::Q));
mod->remove(dlatch);
return true;
}
@@ -269,23 +269,23 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
RTLIL::Const val_cp, val_rp, val_rv, val_ep;
if (dff->type == ID($_FF_)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
}
else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1);
}
else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
- sig_r = dff->getPort(ID(R));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
+ sig_r = dff->getPort(ID::R);
val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1);
@@ -293,39 +293,39 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == 'N' || dff->type[8] == 'P')) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
- sig_e = dff->getPort(ID(E));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
+ sig_e = dff->getPort(ID::E);
val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
}
else if (dff->type == ID($ff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
}
else if (dff->type == ID($dff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
}
else if (dff->type == ID($dffe)) {
- sig_e = dff->getPort(ID(EN));
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
- val_ep = RTLIL::Const(dff->parameters[ID(EN_POLARITY)].as_bool(), 1);
+ sig_e = dff->getPort(ID::EN);
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
+ val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1);
}
else if (dff->type == ID($adff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- sig_r = dff->getPort(ID(ARST));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
- val_rp = RTLIL::Const(dff->parameters[ID(ARST_POLARITY)].as_bool(), 1);
- val_rv = dff->parameters[ID(ARST_VALUE)];
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ sig_r = dff->getPort(ID::ARST);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
+ val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1);
+ val_rv = dff->parameters[ID::ARST_VALUE];
}
else
log_abort();
@@ -422,15 +422,15 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
if (dff->type == ID($adff)) {
dff->type = ID($dff);
- dff->unsetPort(ID(ARST));
- dff->unsetParam(ID(ARST_POLARITY));
- dff->unsetParam(ID(ARST_VALUE));
+ dff->unsetPort(ID::ARST);
+ dff->unsetParam(ID::ARST_POLARITY);
+ dff->unsetParam(ID::ARST_VALUE);
return true;
}
log_assert(dff->type.begins_with("$_DFF_"));
dff->type = stringf("$_DFF_%c_", + dff->type[6]);
- dff->unsetPort(ID(R));
+ dff->unsetPort(ID::R);
}
// If enable signal is present, and is fully constant
@@ -447,14 +447,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
if (dff->type == ID($dffe)) {
dff->type = ID($dff);
- dff->unsetPort(ID(EN));
- dff->unsetParam(ID(EN_POLARITY));
+ dff->unsetPort(ID::EN);
+ dff->unsetParam(ID::EN_POLARITY);
return true;
}
log_assert(dff->type.begins_with("$_DFFE_"));
dff->type = stringf("$_DFF_%c_", + dff->type[7]);
- dff->unsetPort(ID(E));
+ dff->unsetPort(ID::E);
}
if (sat && has_init && (!sig_r.size() || val_init == val_rv))
@@ -509,9 +509,9 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0,
position, log_id(dff), log_id(dff->type), log_id(mod));
- SigSpec tmp = dff->getPort(ID(D));
+ SigSpec tmp = dff->getPort(ID::D);
tmp[position] = sigbit_init_val;
- dff->setPort(ID(D), tmp);
+ dff->setPort(ID::D, tmp);
removed_sigbits = true;
}
@@ -528,7 +528,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
delete_dff:
log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
- remove_init_attr(dff->getPort(ID(Q)));
+ remove_init_attr(dff->getPort(ID::Q));
mod->remove(dff);
for (auto &entry : bit2driver)
@@ -588,8 +588,8 @@ struct OptRmdffPass : public Pass {
for (auto wire : module->wires())
{
- if (wire->attributes.count(ID(init)) != 0) {
- Const initval = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init) != 0) {
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(wire, i), initval[i]);
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index f59f978a6..1f69c98f4 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -98,8 +98,8 @@ struct ExtSigSpec {
bool cell_supported(RTLIL::Cell *cell)
{
if (cell->type.in(ID($alu))) {
- RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
- RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
+ RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
+ RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
@@ -139,7 +139,7 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
if (cell->type == ID($alu) && port_name == ID::B)
- return cell->getPort(ID(BI));
+ return cell->getPort(ID::BI);
else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1);
@@ -190,7 +190,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto shared_op = ports[0].op;
if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
- max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int());
+ max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
for (auto &operand : muxed_operands)
@@ -210,7 +210,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B);
- RTLIL::SigSpec mux_s = mux->getPort(ID(S));
+ RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
RTLIL::SigSpec shared_pmux_b;
@@ -237,7 +237,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b);
mux->setPort(ID::Y, mux_y);
- mux->setPort(ID(S), mux_s);
+ mux->setPort(ID::S, mux_s);
for (const auto &op : muxed_operands)
shared_pmux_b.append(op.sig);
@@ -245,26 +245,26 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
if (shared_op->type.in(ID($alu))) {
- RTLIL::SigSpec alu_x = shared_op->getPort(ID(X));
- RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO));
+ RTLIL::SigSpec alu_x = shared_op->getPort(ID::X);
+ RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO);
- shared_op->setPort(ID(X), alu_x.extract(0, conn_width));
- shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
+ shared_op->setPort(ID::X, alu_x.extract(0, conn_width));
+ shared_op->setPort(ID::CO, alu_co.extract(0, conn_width));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
if (!is_fine)
- shared_op->setParam(ID(Y_WIDTH), conn_width);
+ shared_op->setParam(ID::Y_WIDTH, conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
if (!is_fine)
- shared_op->setParam(ID(B_WIDTH), max_width);
+ shared_op->setParam(ID::B_WIDTH, max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
if (!is_fine)
- shared_op->setParam(ID(A_WIDTH), max_width);
+ shared_op->setParam(ID::A_WIDTH, max_width);
}
}
@@ -452,7 +452,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
- remove_connected_ops(cell->getPort(ID(S)));
+ remove_connected_ops(cell->getPort(ID::S));
find_op_mux_conns(cell);
} else {
for (auto &conn : cell->connections())
@@ -510,7 +510,7 @@ struct OptSharePass : public Pass {
continue;
if (cell->type == ID($alu)) {
- for (RTLIL::IdString port_name : {ID(X), ID(CO)}) {
+ for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
auto mux_insig = assign_map(cell->getPort(port_name));
outsig_to_operator[mux_insig] = cell;
for (auto outbit : mux_insig)
@@ -552,7 +552,7 @@ struct OptSharePass : public Pass {
if (p.mux->type.in(ID($mux), ID($_MUX_)))
mux_port_num = 2;
else
- mux_port_num = p.mux->getPort(ID(S)).size();
+ mux_port_num = p.mux->getPort(ID::S).size();
mux_port_conns.resize(mux_port_num);
}
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 92b5794ac..11b80b6b3 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -46,7 +46,7 @@ struct OnehotDatabase
for (auto wire : module->wires())
{
- auto it = wire->attributes.find(ID(init));
+ auto it = wire->attributes.find(ID::init);
if (it == wire->attributes.end())
continue;
@@ -65,10 +65,10 @@ struct OnehotDatabase
if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
{
- output = cell->getPort(ID(Q));
+ output = cell->getPort(ID::Q);
if (cell->type == ID($adff))
- inputs.push_back(cell->getParam(ID(ARST_VALUE)));
- inputs.push_back(cell->getPort(ID(D)));
+ inputs.push_back(cell->getParam(ID::ARST_VALUE));
+ inputs.push_back(cell->getPort(ID::D));
}
if (cell->type.in(ID($mux), ID($pmux)))
@@ -299,16 +299,16 @@ struct Pmux2ShiftxPass : public Pass {
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
+ bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
+ bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed);
}
@@ -331,7 +331,7 @@ struct Pmux2ShiftxPass : public Pass {
pair<SigSpec, Const> entry;
for (auto it : bits) {
- entry.first.append_bit(it.first);
+ entry.first.append(it.first);
entry.second.bits.push_back(it.second);
}
@@ -352,7 +352,7 @@ struct Pmux2ShiftxPass : public Pass {
pair<SigSpec, Const> entry;
for (auto it : bits) {
- entry.first.append_bit(it.first);
+ entry.first.append(it.first);
entry.second.bits.push_back(it.second);
}
@@ -368,7 +368,7 @@ struct Pmux2ShiftxPass : public Pass {
continue;
string src = cell->get_src_attribute();
- int width = cell->getParam(ID(WIDTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
int width_bits = ceil_log2(width);
int extwidth = width;
@@ -379,7 +379,7 @@ struct Pmux2ShiftxPass : public Pass {
SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B);
- SigSpec S = sigmap(cell->getPort(ID(S)));
+ SigSpec S = sigmap(cell->getPort(ID::S));
for (int i = 0; i < GetSize(S); i++)
{
if (!eqdb.count(S[i]))
@@ -400,7 +400,7 @@ struct Pmux2ShiftxPass : public Pass {
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
- SigSpec updated_S = cell->getPort(ID(S));
+ SigSpec updated_S = cell->getPort(ID::S);
SigSpec updated_B = cell->getPort(ID::B);
while (!seldb.empty())
@@ -727,9 +727,9 @@ struct Pmux2ShiftxPass : public Pass {
}
// update $pmux cell
- cell->setPort(ID(S), updated_S);
+ cell->setPort(ID::S, updated_S);
cell->setPort(ID::B, updated_B);
- cell->setParam(ID(S_WIDTH), GetSize(updated_S));
+ cell->setParam(ID::S_WIDTH, GetSize(updated_S));
}
}
}
@@ -785,16 +785,16 @@ struct OnehotPass : public Pass {
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
+ bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
+ bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed);
}
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 92ce3fd11..2839507b0 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -41,7 +41,8 @@ struct ShareWorkerConfig
struct ShareWorker
{
- ShareWorkerConfig config;
+ const ShareWorkerConfig config;
+ int limit;
pool<RTLIL::IdString> generic_ops;
RTLIL::Design *design;
@@ -49,7 +50,6 @@ struct ShareWorker
CellTypes fwd_ct, cone_ct;
ModWalker modwalker;
- ModIndex mi;
pool<RTLIL::Cell*> cells_to_remove;
pool<RTLIL::Cell*> recursion_state;
@@ -90,7 +90,7 @@ struct ShareWorker
for (auto &pbit : portbits) {
if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
- pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool();
+ pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
@@ -331,7 +331,7 @@ struct ShareWorker
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
- supercell->setParam(ID(Y_WIDTH), width);
+ supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
supermacc.optimize(width);
@@ -369,21 +369,21 @@ struct ShareWorker
}
if (cell->type == ID($memrd)) {
- if (cell->parameters.at(ID(CLK_ENABLE)).as_bool())
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
- if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const())
+ if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
shareable_cells.insert(cell);
continue;
}
if (cell->type.in(ID($mul), ID($div), ID($mod))) {
- if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4)
+ if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
shareable_cells.insert(cell);
continue;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
- if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8)
+ if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
shareable_cells.insert(cell);
continue;
}
@@ -403,7 +403,7 @@ struct ShareWorker
if (c1->type == ID($memrd))
{
- if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string())
+ if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
return false;
return true;
@@ -413,11 +413,11 @@ struct ShareWorker
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
@@ -430,13 +430,13 @@ struct ShareWorker
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
@@ -450,13 +450,13 @@ struct ShareWorker
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
int min1_width = min(a1_width, b1_width);
int max1_width = max(a1_width, b1_width);
@@ -510,21 +510,21 @@ struct ShareWorker
if (config.generic_uni_ops.count(c1->type))
{
- if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
- new_a.append_bit(RTLIL::State::S0);
+ new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
- unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::A_SIGNED) = true;
unsigned_cell->check();
}
- bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
- log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
+ bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
+ log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
@@ -544,9 +544,9 @@ struct ShareWorker
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters[ID(A_SIGNED)] = a_signed;
- supercell->parameters[ID(A_WIDTH)] = a_width;
- supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->parameters[ID::A_SIGNED] = a_signed;
+ supercell->parameters[ID::A_WIDTH] = a_width;
+ supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
@@ -563,11 +563,11 @@ struct ShareWorker
if (config.generic_cbin_ops.count(c1->type))
{
- int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) +
- max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int());
+ int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
+ max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
- int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) +
- max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int());
+ int score_flipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()) +
+ max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int());
if (score_flipped < score_unflipped)
{
@@ -575,36 +575,36 @@ struct ShareWorker
c2->setPort(ID::A, c2->getPort(ID::B));
c2->setPort(ID::B, tmp);
- std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH)));
- std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED)));
+ std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH));
+ std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED));
modified_src_cells = true;
}
}
- if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
- new_a.append_bit(RTLIL::State::S0);
+ new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
- unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::A_SIGNED) = true;
modified_src_cells = true;
}
- if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
- new_b.append_bit(RTLIL::State::S0);
+ new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b);
}
- unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::B_SIGNED) = true;
modified_src_cells = true;
}
@@ -613,11 +613,11 @@ struct ShareWorker
c2->check();
}
- bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
- bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool();
+ bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
+ bool b_signed = c1->parameters.at(ID::B_SIGNED).as_bool();
- log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
- log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool());
+ log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
+ log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false;
@@ -664,32 +664,32 @@ struct ShareWorker
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters[ID(A_SIGNED)] = a_signed;
- supercell->parameters[ID(B_SIGNED)] = b_signed;
- supercell->parameters[ID(A_WIDTH)] = a_width;
- supercell->parameters[ID(B_WIDTH)] = b_width;
- supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->parameters[ID::A_SIGNED] = a_signed;
+ supercell->parameters[ID::B_SIGNED] = b_signed;
+ supercell->parameters[ID::A_WIDTH] = a_width;
+ supercell->parameters[ID::B_WIDTH] = b_width;
+ supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci));
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi));
- supercell->setPort(ID(CI), ci);
- supercell->setPort(ID(BI), bi);
- supercell->setPort(ID(CO), co);
- supercell->setPort(ID(X), x);
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
+ supercell->setPort(ID::CI, ci);
+ supercell->setPort(ID::BI, bi);
+ supercell->setPort(ID::CO, co);
+ supercell->setPort(ID::X, x);
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
if (c1->type == ID($alu)) {
- supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO))));
- supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO))));
- supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X))));
- supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X))));
+ supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
+ supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
}
supercell_aux.insert(supercell);
@@ -708,15 +708,15 @@ struct ShareWorker
if (c1->type == ID($memrd))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
- RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR));
- RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR));
+ RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
+ RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
- supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
- supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1));
- supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA))));
+ supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
+ supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
+ supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
@@ -747,8 +747,8 @@ struct ShareWorker
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
for (auto &bit : pbits) {
- if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S))
- forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1));
+ if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S)
+ forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
@@ -790,7 +790,7 @@ struct ShareWorker
p.second.bits.clear();
for (auto &it : p_bits) {
- p.first.append_bit(it.first);
+ p.first.append(it.first);
p.second.bits.push_back(it.second);
}
@@ -890,10 +890,10 @@ struct ShareWorker
bool used_in_a = false;
std::set<int> used_in_b_parts;
- int width = c->parameters.at(ID(WIDTH)).as_int();
+ int width = c->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B));
- std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S)));
+ std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))
@@ -906,14 +906,14 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
- p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
+ p.first.append(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
- p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
+ p.first.append(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
}
@@ -948,7 +948,7 @@ struct ShareWorker
RTLIL::SigSpec signal;
for (auto &bit : all_bits)
- signal.append_bit(bit);
+ signal.append(bit);
return signal;
}
@@ -963,7 +963,7 @@ struct ShareWorker
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
- new_p.first.append_bit(p_first[i]);
+ new_p.first.append(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
}
@@ -1071,6 +1071,8 @@ struct ShareWorker
ct.setup_internals();
ct.setup_stdcells();
+ ModIndex mi(module);
+
pool<RTLIL::Cell*> queue, covered;
queue.insert(cell);
@@ -1117,13 +1119,9 @@ struct ShareWorker
module->remove(cell);
}
- ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
- config(config), design(design), module(module), mi(module)
+ ShareWorker(ShareWorkerConfig config, RTLIL::Design* design) :
+ config(config), design(design), modwalker(design)
{
- #ifndef NDEBUG
- bool before_scc = module_has_scc();
- #endif
-
generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
@@ -1140,8 +1138,27 @@ struct ShareWorker
cone_ct.cell_types.erase(ID($shr));
cone_ct.cell_types.erase(ID($sshl));
cone_ct.cell_types.erase(ID($sshr));
+ }
- modwalker.setup(design, module);
+ void operator()(RTLIL::Module *module) {
+ this->module = module;
+
+ #ifndef NDEBUG
+ bool before_scc = module_has_scc();
+ #endif
+
+ limit = config.limit;
+ modwalker.setup(module);
+
+ cells_to_remove.clear();
+ recursion_state.clear();
+ topo_cell_drivers.clear();
+ topo_bit_drivers.clear();
+ exclusive_ctrls.clear();
+ terminal_bits.clear();
+ shareable_cells.clear();
+ forbidden_controls_cache.clear();
+ activation_patterns_cache.clear();
find_terminal_bits();
find_shareable_cells();
@@ -1154,8 +1171,8 @@ struct ShareWorker
for (auto cell : module->cells())
if (cell->type == ID($pmux))
- for (auto bit : cell->getPort(ID(S)))
- for (auto other_bit : cell->getPort(ID(S)))
+ for (auto bit : cell->getPort(ID::S))
+ for (auto other_bit : cell->getPort(ID::S))
if (bit < other_bit)
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
@@ -1399,8 +1416,8 @@ struct ShareWorker
topo_cell_drivers[cell] = { supercell };
topo_cell_drivers[other_cell] = { supercell };
- if (config.limit > 0)
- config.limit--;
+ if (limit > 0)
+ limit--;
break;
}
@@ -1528,9 +1545,10 @@ struct SharePass : public Pass {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- ShareWorker(config, design, mod_it.second);
+ ShareWorker sw(config, design);
+
+ for (auto module : design->selected_modules())
+ sw(module);
}
} SharePass;
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 04b882db9..195400bf0 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -65,7 +65,7 @@ struct WreduceWorker
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
- SigSpec sig_s = mi.sigmap(cell->getPort(ID(S)));
+ SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
std::vector<SigBit> bits_removed;
@@ -98,7 +98,7 @@ struct WreduceWorker
SigSpec sig_removed;
for (int i = GetSize(bits_removed)-1; i >= 0; i--)
- sig_removed.append_bit(bits_removed[i]);
+ sig_removed.append(bits_removed[i]);
if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
@@ -141,8 +141,8 @@ struct WreduceWorker
{
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
- SigSpec sig_d = mi.sigmap(cell->getPort(ID(D)));
- SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q)));
+ SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
+ SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
bool is_adff = (cell->type == ID($adff));
Const initval, arst_value;
@@ -151,8 +151,8 @@ struct WreduceWorker
if (width_before == 0)
return;
- if (cell->parameters.count(ID(ARST_VALUE))) {
- arst_value = cell->parameters[ID(ARST_VALUE)];
+ if (cell->parameters.count(ID::ARST_VALUE)) {
+ arst_value = cell->parameters[ID::ARST_VALUE];
}
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
@@ -220,13 +220,13 @@ struct WreduceWorker
work_queue_bits.insert(bit);
// Narrow ARST_VALUE parameter to new size.
- if (cell->parameters.count(ID(ARST_VALUE))) {
+ if (cell->parameters.count(ID::ARST_VALUE)) {
arst_value.bits.resize(GetSize(sig_q));
- cell->setParam(ID(ARST_VALUE), arst_value);
+ cell->setParam(ID::ARST_VALUE, arst_value);
}
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->fixup_parameters();
}
@@ -306,8 +306,8 @@ struct WreduceWorker
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam(ID(A_SIGNED), 0);
- cell->setParam(ID(B_SIGNED), 0);
+ cell->setParam(ID::A_SIGNED, 0);
+ cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
port_b_signed = false;
did_something = true;
@@ -319,7 +319,7 @@ struct WreduceWorker
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam(ID(A_SIGNED), 0);
+ cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false;
did_something = true;
}
@@ -349,7 +349,7 @@ struct WreduceWorker
if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
{
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub);
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0;
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
@@ -392,8 +392,8 @@ struct WreduceWorker
static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count(ID(src));
- count -= w->attributes.count(ID(unused_bits));
+ count -= w->attributes.count(ID::src);
+ count -= w->attributes.count(ID::unused_bits);
return count;
}
@@ -406,8 +406,8 @@ struct WreduceWorker
if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
- if (w->attributes.count(ID(init))) {
- Const initval = w->attributes.at(ID(init));
+ if (w->attributes.count(ID::init)) {
+ Const initval = w->attributes.at(ID::init);
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++)
@@ -464,8 +464,8 @@ struct WreduceWorker
if (!remove_init_bits.empty()) {
for (auto w : module->wires()) {
- if (w->attributes.count(ID(init))) {
- Const initval = w->attributes.at(ID(init));
+ if (w->attributes.count(ID::init)) {
+ Const initval = w->attributes.at(ID::init);
Const new_initval(State::Sx, GetSize(w));
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
@@ -473,7 +473,7 @@ struct WreduceWorker
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
- w->attributes.at(ID(init)) = new_initval;
+ w->attributes.at(ID::init) = new_initval;
}
}
}
@@ -539,7 +539,7 @@ struct WreducePass : public Pass {
SigSpec sig = c->getPort(ID::Y);
if (!sig.has_const()) {
c->setPort(ID::Y, sig[0]);
- c->setParam(ID(Y_WIDTH), 1);
+ c->setParam(ID::Y_WIDTH, 1);
sig.remove(0);
module->connect(sig, Const(0, GetSize(sig)));
}
@@ -549,7 +549,7 @@ struct WreducePass : public Pass {
{
SigSpec A = c->getPort(ID::A);
int original_a_width = GetSize(A);
- if (c->getParam(ID(A_SIGNED)).as_bool()) {
+ if (c->getParam(ID::A_SIGNED).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
A.remove(GetSize(A)-1, 1);
} else {
@@ -560,12 +560,12 @@ struct WreducePass : public Pass {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::A, A);
- c->setParam(ID(A_WIDTH), GetSize(A));
+ c->setParam(ID::A_WIDTH, GetSize(A));
}
SigSpec B = c->getPort(ID::B);
int original_b_width = GetSize(B);
- if (c->getParam(ID(B_SIGNED)).as_bool()) {
+ if (c->getParam(ID::B_SIGNED).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
B.remove(GetSize(B)-1, 1);
} else {
@@ -576,23 +576,23 @@ struct WreducePass : public Pass {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::B, B);
- c->setParam(ID(B_WIDTH), GetSize(B));
+ c->setParam(ID::B_WIDTH, GetSize(B));
}
}
if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
- IdString memid = c->getParam(ID(MEMID)).decode_string();
+ IdString memid = c->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
- int cur_addrbits = c->getParam(ID(ABITS)).as_int();
+ int cur_addrbits = c->getParam(ID::ABITS).as_int();
int max_addrbits = ceil_log2(mem->start_offset + mem->size);
if (cur_addrbits > max_addrbits) {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
- c->setParam(ID(ABITS), max_addrbits);
- c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits));
+ c->setParam(ID::ABITS, max_addrbits);
+ c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 13:59:39 +0000