diff options
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 13 | ||||
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 711 | ||||
| -rw-r--r-- | passes/opt/opt_share.cc | 361 |
4 files changed, 147 insertions, 939 deletions
diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 64fee76b3..4ae9b8895 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -4,7 +4,6 @@ OBJS += passes/opt/opt_merge.o OBJS += passes/opt/opt_mem.o OBJS += passes/opt/opt_muxtree.o OBJS += passes/opt/opt_reduce.o -OBJS += passes/opt/opt_rmdff.o OBJS += passes/opt/opt_dff.o OBJS += passes/opt/opt_share.o OBJS += passes/opt/opt_clean.o diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 44de60b48..5370881d3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -55,7 +55,12 @@ struct keep_cache_t if (!module->get_bool_attribute(ID::keep)) { bool found_keep = false; for (auto cell : module->cells()) - if (query(cell, true /* ignore_specify */)) { + if (query(cell, true /* ignore_specify_mem */)) { + found_keep = true; + break; + } + for (auto wire : module->wires()) + if (wire->get_bool_attribute(ID::keep)) { found_keep = true; break; } @@ -65,12 +70,12 @@ struct keep_cache_t return cache[module]; } - bool query(Cell *cell, bool ignore_specify = false) + bool query(Cell *cell, bool ignore_specify_mem = false) { - if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) + if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) return true; - if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule))) + if (!ignore_specify_mem && cell->type.in(ID($memwr), ID($meminit), ID($specify2), ID($specify3), ID($specrule))) return true; if (cell->has_keep_attr()) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc deleted file mode 100644 index 8f7628a4a..000000000 --- a/passes/opt/opt_rmdff.cc +++ /dev/null @@ -1,711 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/log.h" -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/satgen.h" -#include "kernel/sigtools.h" -#include <stdio.h> -#include <stdlib.h> - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -SigMap assign_map, dff_init_map; -SigSet<RTLIL::Cell*> mux_drivers; -dict<SigBit, RTLIL::Cell*> bit2driver; -dict<SigBit, pool<SigBit>> init_attributes; - -bool keepdc; -bool sat; - -void remove_init_attr(SigSpec sig) -{ - for (auto bit : assign_map(sig)) - if (init_attributes.count(bit)) - for (auto wbit : init_attributes.at(bit)) - wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx; -} - -bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) -{ - SigSpec sig_set, sig_clr; - State pol_set, pol_clr; - - if (cell->hasPort(ID::S)) - sig_set = cell->getPort(ID::S); - - if (cell->hasPort(ID::R)) - sig_clr = cell->getPort(ID::R); - - if (cell->hasPort(ID::SET)) - sig_set = cell->getPort(ID::SET); - - if (cell->hasPort(ID::CLR)) - sig_clr = cell->getPort(ID::CLR); - - log_assert(GetSize(sig_set) == GetSize(sig_clr)); - - if (cell->type.begins_with("$_DFFSR_")) { - pol_set = cell->type[9] == 'P' ? State::S1 : State::S0; - pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0; - } else - if (cell->type.begins_with("$_DLATCHSR_")) { - pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; - pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; - } else - if (cell->type.in(ID($dffsr), ID($dlatchsr))) { - pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0; - pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0; - } else - log_abort(); - - State npol_set = pol_set == State::S0 ? State::S1 : State::S0; - State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0; - - SigSpec sig_d = cell->getPort(ID::D); - SigSpec sig_q = cell->getPort(ID::Q); - - bool did_something = false; - bool proper_sr = false; - bool used_pol_set = false; - bool used_pol_clr = false; - bool hasreset = false; - Const reset_val; - SigSpec sig_reset; - - for (int i = 0; i < GetSize(sig_set); i++) - { - SigBit s = sig_set[i], c = sig_clr[i]; - - if (s != npol_set || c != npol_clr) - hasreset = true; - - if (s == pol_set || c == pol_clr) - { - log("Constantly %s Q bit %s for SR cell %s (%s) from module %s.\n", - s == pol_set ? "set" : "cleared", log_signal(sig_q[i]), - log_id(cell), log_id(cell->type), log_id(mod)); - - remove_init_attr(sig_q[i]); - mod->connect(sig_q[i], s == pol_set ? State::S1 : State::S0); - sig_set.remove(i); - sig_clr.remove(i); - sig_d.remove(i); - sig_q.remove(i--); - did_something = true; - continue; - } - if (sig_reset.empty() && s.wire != nullptr) sig_reset = s; - if (sig_reset.empty() && c.wire != nullptr) sig_reset = c; - - if (s.wire != nullptr && s != sig_reset) proper_sr = true; - if (c.wire != nullptr && c != sig_reset) proper_sr = true; - - if ((s.wire == nullptr) != (c.wire == nullptr)) { - if (s.wire != nullptr) used_pol_set = true; - if (c.wire != nullptr) used_pol_clr = true; - reset_val.bits.push_back(c.wire == nullptr ? State::S1 : State::S0); - } else - proper_sr = true; - } - - if (!hasreset) - proper_sr = false; - - if (GetSize(sig_set) == 0) - { - log("Removing %s (%s) from module %s.\n", log_id(cell), log_id(cell->type), log_id(mod)); - mod->remove(cell); - return true; - } - - if (cell->type.in(ID($dffsr), ID($dlatchsr))) - { - cell->setParam(ID::WIDTH, GetSize(sig_d)); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - } - else - { - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - } - - if (proper_sr) - return did_something; - - if (used_pol_set && used_pol_clr && pol_set != pol_clr) - return did_something; - - if (cell->type == ID($dlatchsr)) - return did_something; - - State unified_pol = used_pol_set ? pol_set : pol_clr; - - if (cell->type == ID($dffsr)) - { - if (hasreset) - { - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod)); - - cell->type = ID($adff); - cell->setParam(ID::ARST_POLARITY, unified_pol); - cell->setParam(ID::ARST_VALUE, reset_val); - cell->setPort(ID::ARST, sig_reset); - - cell->unsetParam(ID::SET_POLARITY); - cell->unsetParam(ID::CLR_POLARITY); - cell->unsetPort(ID::SET); - cell->unsetPort(ID::CLR); - } - else - { - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod)); - - cell->type = ID($dff); - cell->unsetParam(ID::SET_POLARITY); - cell->unsetParam(ID::CLR_POLARITY); - cell->unsetPort(ID::SET); - cell->unsetPort(ID::CLR); - } - - return true; - } - - if (!hasreset) - { - IdString new_type; - - if (cell->type.begins_with("$_DFFSR_")) - new_type = stringf("$_DFF_%c_", cell->type[8]); - else if (cell->type.begins_with("$_DLATCHSR_")) - new_type = stringf("$_DLATCH_%c_", cell->type[11]); - else - log_abort(); - - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod)); - - cell->type = new_type; - cell->unsetPort(ID::S); - cell->unsetPort(ID::R); - - return true; - } - - return did_something; -} - -bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) -{ - SigSpec sig_e; - State on_state, off_state; - - if (dlatch->type == ID($dlatch)) { - sig_e = assign_map(dlatch->getPort(ID::EN)); - on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0; - off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1; - } else - if (dlatch->type == ID($_DLATCH_P_)) { - sig_e = assign_map(dlatch->getPort(ID::E)); - on_state = State::S1; - off_state = State::S0; - } else - if (dlatch->type == ID($_DLATCH_N_)) { - sig_e = assign_map(dlatch->getPort(ID::E)); - on_state = State::S0; - off_state = State::S1; - } else - log_abort(); - - if (sig_e == off_state) - { - RTLIL::Const val_init; - for (auto bit : dff_init_map(dlatch->getPort(ID::Q))) - val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx); - mod->connect(dlatch->getPort(ID::Q), val_init); - goto delete_dlatch; - } - - if (sig_e == on_state) - { - mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D)); - goto delete_dlatch; - } - - return false; - -delete_dlatch: - log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod)); - remove_init_attr(dlatch->getPort(ID::Q)); - mod->remove(dlatch); - return true; -} - -bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) -{ - RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e; - RTLIL::Const val_cp, val_rp, val_rv, val_ep; - - if (dff->type == ID($_FF_)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - } - else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1); - } - else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 && - (dff->type[6] == 'N' || dff->type[6] == 'P') && - (dff->type[7] == 'N' || dff->type[7] == 'P') && - (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - sig_r = dff->getPort(ID::R); - val_cp = RTLIL::Const(dff->type[6] == 'P', 1); - val_rp = RTLIL::Const(dff->type[7] == 'P', 1); - val_rv = RTLIL::Const(dff->type[8] == '1', 1); - } - else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 && - (dff->type[7] == 'N' || dff->type[7] == 'P') && - (dff->type[8] == 'N' || dff->type[8] == 'P')) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - sig_e = dff->getPort(ID::E); - val_cp = RTLIL::Const(dff->type[7] == 'P', 1); - val_ep = RTLIL::Const(dff->type[8] == 'P', 1); - } - else if (dff->type == ID($ff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - } - else if (dff->type == ID($dff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - } - else if (dff->type == ID($dffe)) { - sig_e = dff->getPort(ID::EN); - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1); - } - else if (dff->type == ID($adff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - sig_r = dff->getPort(ID::ARST); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1); - val_rv = dff->parameters[ID::ARST_VALUE]; - } - else - log_abort(); - - assign_map.apply(sig_d); - assign_map.apply(sig_q); - assign_map.apply(sig_c); - assign_map.apply(sig_r); - - bool has_init = false; - RTLIL::Const val_init; - for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) { - if (bit.wire == NULL || keepdc) - has_init = true; - val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx); - } - - if (dff->type.in(ID($ff), ID($dff)) && mux_drivers.has(sig_d)) { - std::set<RTLIL::Cell*> muxes; - mux_drivers.find(sig_d, muxes); - for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID::A)); - RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID::B)); - if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) { - mod->connect(sig_q, sig_b); - goto delete_dff; - } - if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) { - mod->connect(sig_q, sig_a); - goto delete_dff; - } - } - } - - // If clock is driven by a constant and (i) no reset signal - // (ii) Q has no initial value - // (iii) initial value is same as reset value - if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) { - if (val_rv.bits.size() == 0) - val_rv = val_init; - // Q is permanently reset value or initial value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - // If D is fully undefined and reset signal present and (i) Q has no initial value - // (ii) initial value is same as reset value - if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) { - // Q is permanently reset value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - // If D is fully undefined and no reset signal and Q has an initial value - if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { - // Q is permanently initial value - mod->connect(sig_q, val_init); - goto delete_dff; - } - - // If D is fully constant and (i) no reset signal - // (ii) reset value is same as constant D - // and (a) has no initial value - // (b) initial value same as constant D - if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { - // Q is permanently D - mod->connect(sig_q, sig_d); - goto delete_dff; - } - - // If D input is same as Q output and (i) no reset signal - // (ii) no initial signal - // (iii) initial value is same as reset value - if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) { - // Q is permanently reset value or initial value - if (sig_r.size()) - mod->connect(sig_q, val_rv); - else if (has_init) - mod->connect(sig_q, val_init); - goto delete_dff; - } - - // If reset signal is present, and is fully constant - if (!sig_r.empty() && sig_r.is_fully_const()) - { - // If reset value is permanently active or if reset is undefined - if (sig_r == val_rp || sig_r.is_fully_undef()) { - // Q is permanently reset value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - - if (dff->type == ID($adff)) { - dff->type = ID($dff); - dff->unsetPort(ID::ARST); - dff->unsetParam(ID::ARST_POLARITY); - dff->unsetParam(ID::ARST_VALUE); - return true; - } - - log_assert(dff->type.begins_with("$_DFF_")); - dff->type = stringf("$_DFF_%c_", + dff->type[6]); - dff->unsetPort(ID::R); - } - - // If enable signal is present, and is fully constant - if (!sig_e.empty() && sig_e.is_fully_const()) - { - // If enable value is permanently inactive - if (sig_e != val_ep) { - // Q is permanently initial value - mod->connect(sig_q, val_init); - goto delete_dff; - } - - log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - - if (dff->type == ID($dffe)) { - dff->type = ID($dff); - dff->unsetPort(ID::EN); - dff->unsetParam(ID::EN_POLARITY); - return true; - } - - log_assert(dff->type.begins_with("$_DFFE_")); - dff->type = stringf("$_DFF_%c_", + dff->type[7]); - dff->unsetPort(ID::E); - } - - if (sat && has_init && (!sig_r.size() || val_init == val_rv)) - { - bool removed_sigbits = false; - - ezSatPtr ez; - SatGen satgen(ez.get(), &assign_map); - pool<Cell*> sat_cells; - - std::function<void(Cell*)> sat_import_cell = [&](Cell *c) { - if (!sat_cells.insert(c).second) - return; - if (!satgen.importCell(c)) - return; - for (auto &conn : c->connections()) { - if (!c->input(conn.first)) - continue; - for (auto bit : assign_map(conn.second)) - if (bit2driver.count(bit)) - sat_import_cell(bit2driver.at(bit)); - } - }; - - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - for (int position = 0; position < GetSize(sig_d); position += 1) { - RTLIL::SigBit q_sigbit = sig_q[position]; - RTLIL::SigBit d_sigbit = sig_d[position]; - - if ((!q_sigbit.wire) || (!d_sigbit.wire)) - continue; - - if (!bit2driver.count(d_sigbit)) - continue; - - sat_import_cell(bit2driver.at(d_sigbit)); - - RTLIL::State sigbit_init_val = val_init[position]; - if (sigbit_init_val != State::S0 && sigbit_init_val != State::S1) - continue; - - int init_sat_pi = satgen.importSigSpec(sigbit_init_val).front(); - int q_sat_pi = satgen.importSigBit(q_sigbit); - int d_sat_pi = satgen.importSigBit(d_sigbit); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = ez->solve(ez->IFF(q_sat_pi, init_sat_pi), ez->NOT(ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (!counter_example_found) - { - log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0, - position, log_id(dff), log_id(dff->type), log_id(mod)); - - SigSpec tmp = dff->getPort(ID::D); - tmp[position] = sigbit_init_val; - dff->setPort(ID::D, tmp); - - removed_sigbits = true; - } - } - - if (removed_sigbits) { - handle_dff(mod, dff); - return true; - } - } - - - return false; - -delete_dff: - log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - remove_init_attr(dff->getPort(ID::Q)); - mod->remove(dff); - - for (auto &entry : bit2driver) - if (entry.second == dff) - bit2driver.erase(entry.first); - - return true; -} - -struct OptRmdffPass : public Pass { - OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" opt_rmdff [-keepdc] [-sat] [selection]\n"); - log("\n"); - log("This pass identifies flip-flops with constant inputs and replaces them with\n"); - log("a constant driver.\n"); - log("\n"); - log(" -sat\n"); - log(" additionally invoke SAT solver to detect and remove flip-flops (with \n"); - log(" non-constant inputs) that can also be replaced with a constant driver\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - int total_count = 0, total_initdrv = 0; - log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n"); - - keepdc = false; - sat = false; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-keepdc") { - keepdc = true; - continue; - } - if (args[argidx] == "-sat") { - sat = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - for (auto module : design->selected_modules()) { - pool<SigBit> driven_bits; - dict<SigBit, State> init_bits; - - assign_map.set(module); - dff_init_map.set(module); - mux_drivers.clear(); - bit2driver.clear(); - init_attributes.clear(); - - for (auto wire : module->wires()) - { - if (wire->attributes.count(ID::init) != 0) { - Const initval = wire->attributes.at(ID::init); - for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) - if (initval[i] == State::S0 || initval[i] == State::S1) - dff_init_map.add(SigBit(wire, i), initval[i]); - for (int i = 0; i < GetSize(wire); i++) { - SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit); - if (mapped_bit.wire) { - init_attributes[mapped_bit].insert(wire_bit); - if (i < GetSize(initval)) - init_bits[mapped_bit] = initval[i]; - } - } - } - - if (wire->port_input) { - for (auto bit : assign_map(wire)) - driven_bits.insert(bit); - } - } - - std::vector<RTLIL::IdString> dff_list; - std::vector<RTLIL::IdString> dffsr_list; - std::vector<RTLIL::IdString> dlatch_list; - for (auto cell : module->cells()) - { - for (auto &conn : cell->connections()) { - bool is_output = cell->output(conn.first); - if (is_output || !cell->known()) - for (auto bit : assign_map(conn.second)) { - if (is_output) - bit2driver[bit] = cell; - driven_bits.insert(bit); - } - } - - if (cell->type.in(ID($mux), ID($pmux))) { - if (cell->getPort(ID::A).size() == cell->getPort(ID::B).size()) - mux_drivers.insert(assign_map(cell->getPort(ID::Y)), cell); - continue; - } - - if (!design->selected(module, cell)) - continue; - - if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_), - ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_), ID($dffsr), - ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_), - ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_), ID($dlatchsr))) - dffsr_list.push_back(cell->name); - - if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), - ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), - ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_), - ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), - ID($ff), ID($dff), ID($dffe), ID($adff))) - dff_list.push_back(cell->name); - - if (cell->type.in(ID($dlatch), ID($_DLATCH_P_), ID($_DLATCH_N_))) - dlatch_list.push_back(cell->name); - } - - for (auto &id : dffsr_list) { - if (module->cell(id) != nullptr && - handle_dffsr(module, module->cells_[id])) - total_count++; - } - - for (auto &id : dff_list) { - if (module->cell(id) != nullptr && - handle_dff(module, module->cells_[id])) - total_count++; - } - - for (auto &id : dlatch_list) { - if (module->cell(id) != nullptr && - handle_dlatch(module, module->cells_[id])) - total_count++; - } - - SigSpec const_init_sigs; - - for (auto bit : init_bits) - if (!driven_bits.count(bit.first)) - const_init_sigs.append(bit.first); - - const_init_sigs.sort_and_unify(); - - for (SigSpec sig : const_init_sigs.chunks()) - { - Const val; - - for (auto bit : sig) - val.bits.push_back(init_bits.at(bit)); - - log("Promoting init spec %s = %s to constant driver in module %s.\n", - log_signal(sig), log_signal(val), log_id(module)); - - module->connect(sig, val); - remove_init_attr(sig); - total_initdrv++; - } - } - - assign_map.clear(); - mux_drivers.clear(); - bit2driver.clear(); - init_attributes.clear(); - - if (total_count || total_initdrv) - design->scratchpad_set_bool("opt.did_something", true); - - if (total_initdrv) - log("Promoted %d init specs to constant drivers.\n", total_initdrv); - - if (total_count) - log("Replaced %d DFF cells.\n", total_count); - } -} OptRmdffPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index db21cef28..53296699c 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -30,8 +30,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -SigMap assign_map; - struct OpMuxConn { RTLIL::SigSpec sig; RTLIL::Cell *mux; @@ -157,9 +155,9 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name) return false; } -ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sigmap) +ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap) { - auto sig = (*sigmap)(cell->getPort(port_name)); + auto sig = sigmap(cell->getPort(port_name)); RTLIL::SigSpec sign = decode_port_sign(cell, port_name); RTLIL::IdString semantics = decode_port_semantics(cell, port_name); @@ -169,7 +167,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sig return ExtSigSpec(sig, sign, is_signed, semantics); } -void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand) +void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap) { std::vector<ExtSigSpec> muxed_operands; int max_width = 0; @@ -177,10 +175,10 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto op = p.op; RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, &assign_map) == operand) + if (decode_port(op, ID::A, sigmap) == operand) muxed_port_name = ID::B; - auto operand = decode_port(op, muxed_port_name, &assign_map); + auto operand = decode_port(op, muxed_port_name, sigmap); if (operand.sig.size() > max_width) max_width = operand.sig.size(); @@ -190,11 +188,13 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto shared_op = ports[0].op; if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; })) - max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int()); - + max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int()); - for (auto &operand : muxed_operands) + for (auto &operand : muxed_operands) { operand.sig.extend_u0(max_width, operand.is_signed); + if (operand.sign != muxed_operands[0].sign) + operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed)); + } for (const auto& p : ports) { auto op = p.op; @@ -203,61 +203,58 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< module->remove(op); } - for (auto &muxed_op : muxed_operands) - if (muxed_op.sign != muxed_operands[0].sign) - muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed)); - - RTLIL::SigSpec mux_y = mux->getPort(ID::Y); RTLIL::SigSpec mux_a = mux->getPort(ID::A); RTLIL::SigSpec mux_b = mux->getPort(ID::B); RTLIL::SigSpec mux_s = mux->getPort(ID::S); + int conn_width = ports[0].sig.size(); + int conn_mux_offset = ports[0].mux_port_offset; + int conn_op_offset = ports[0].op_outsig_offset; + RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width); RTLIL::SigSpec shared_pmux_b; RTLIL::SigSpec shared_pmux_s; - int conn_width = ports[0].sig.size(); - int conn_offset = ports[0].mux_port_offset; - - shared_op->setPort(ID::Y, shared_op->getPort(ID::Y).extract(0, conn_width)); + // Make a new wire to avoid false equivalence with whatever the former shared output was connected to. + Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width); + SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width); - if (mux->type == ID($pmux)) { - shared_pmux_s = RTLIL::SigSpec(); - - for (const auto &p : ports) { + for (int i = 0; i < GetSize(ports); i++) { + auto &p = ports[i]; + auto &op = muxed_operands[i]; + if (p.mux_port_id == GetSize(mux_s)) { + shared_pmux_a = op.sig; + mux_a.replace(conn_mux_offset, new_sig_out); + } else { shared_pmux_s.append(mux_s[p.mux_port_id]); - mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID::Y)); + shared_pmux_b.append(op.sig); + mux_b.replace(p.mux_port_id * mux_a.size() + conn_mux_offset, new_sig_out); } - } else { - shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)}; - mux_a.replace(conn_offset, shared_op->getPort(ID::Y)); - mux_b.replace(conn_offset, shared_op->getPort(ID::Y)); } mux->setPort(ID::A, mux_a); mux->setPort(ID::B, mux_b); - mux->setPort(ID::Y, mux_y); mux->setPort(ID::S, mux_s); - for (const auto &op : muxed_operands) - shared_pmux_b.append(op.sig); - - auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + SigSpec mux_to_oper; + if (GetSize(shared_pmux_s) == 1) { + mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + } else { + mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + } if (shared_op->type.in(ID($alu))) { - RTLIL::SigSpec alu_x = shared_op->getPort(ID::X); - RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO); - - shared_op->setPort(ID::X, alu_x.extract(0, conn_width)); - shared_op->setPort(ID::CO, alu_co.extract(0, conn_width)); + shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out))); + shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); + shared_op->setPort(ID::Y, new_out); if (!is_fine) - shared_op->setParam(ID::Y_WIDTH, conn_width); + shared_op->setParam(ID::Y_WIDTH, GetSize(new_out)); - if (decode_port(shared_op, ID::A, &assign_map) == operand) { + if (decode_port(shared_op, ID::A, sigmap) == operand) { shared_op->setPort(ID::B, mux_to_oper); if (!is_fine) shared_op->setParam(ID::B_WIDTH, max_width); @@ -275,17 +272,7 @@ typedef struct { } merged_op_t; -template <typename T> void remove_val(std::vector<T> &v, const std::vector<T> &vals) -{ - auto val_iter = vals.rbegin(); - for (auto i = v.rbegin(); i != v.rend(); ++i) - if ((val_iter != vals.rend()) && (*i == *val_iter)) { - v.erase(i.base() - 1); - ++val_iter; - } -} - -void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand) +void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand, const SigMap &sigmap) { auto it = ports.begin(); ExtSigSpec seed; @@ -295,11 +282,11 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe auto op = p->op; RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, &assign_map) == shared_operand) { + if (decode_port(op, ID::A, sigmap) == shared_operand) { muxed_port_name = ID::B; } - auto operand = decode_port(op, muxed_port_name, &assign_map); + auto operand = decode_port(op, muxed_port_name, sigmap); if (seed.empty()) seed = operand; @@ -312,7 +299,7 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe } } -ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users) +ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users, const SigMap &sigmap) { std::set<RTLIL::Cell *> ops_using_operand; std::set<RTLIL::Cell *> ops_set; @@ -324,7 +311,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon auto op_a = seed->op; for (RTLIL::IdString port_name : {ID::A, ID::B}) { - oper = decode_port(op_a, port_name, &assign_map); + oper = decode_port(op_a, port_name, sigmap); auto operand_users = operand_to_users.at(oper); if (operand_users.size() == 1) @@ -345,132 +332,6 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon return ExtSigSpec(); } -dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig, - dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator, - dict<RTLIL::SigBit, RTLIL::SigSpec> &op_aux_to_outsig) -{ - dict<RTLIL::SigSpec, int> op_outsig_user_track; - dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map; - - std::function<void(RTLIL::SigSpec)> remove_outsig = [&](RTLIL::SigSpec outsig) { - for (auto op_outbit : outsig) - op_outbit_to_outsig.erase(op_outbit); - - if (op_mux_conn_map.count(outsig)) - op_mux_conn_map.erase(outsig); - }; - - std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) { - auto aux_outsig = op_aux_to_outsig.at(auxbit); - auto op = outsig_to_operator.at(aux_outsig); - auto op_outsig = assign_map(op->getPort(ID::Y)); - remove_outsig(op_outsig); - - for (auto aux_outbit : aux_outsig) - op_aux_to_outsig.erase(aux_outbit); - }; - - std::function<void(RTLIL::Cell *)> find_op_mux_conns = [&](RTLIL::Cell *mux) { - RTLIL::SigSpec sig; - int mux_port_size; - - if (mux->type.in(ID($mux), ID($_MUX_))) { - mux_port_size = mux->getPort(ID::A).size(); - sig = RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)}; - } else { - mux_port_size = mux->getPort(ID::A).size(); - sig = mux->getPort(ID::B); - } - - auto mux_insig = assign_map(sig); - - for (int i = 0; i < mux_insig.size(); ++i) { - if (op_aux_to_outsig.count(mux_insig[i])) { - remove_outsig_from_aux_bit(mux_insig[i]); - continue; - } - - if (!op_outbit_to_outsig.count(mux_insig[i])) - continue; - - auto op_outsig = op_outbit_to_outsig.at(mux_insig[i]); - - if (op_mux_conn_map.count(op_outsig)) { - remove_outsig(op_outsig); - continue; - } - - int mux_port_id = i / mux_port_size; - int mux_port_offset = i % mux_port_size; - - int op_outsig_offset; - for (op_outsig_offset = 0; op_outsig[op_outsig_offset] != mux_insig[i]; ++op_outsig_offset) - ; - - int j = op_outsig_offset; - do { - if (!op_outbit_to_outsig.count(mux_insig[i])) - break; - - if (op_outbit_to_outsig.at(mux_insig[i]) != op_outsig) - break; - - ++i; - ++j; - } while ((i / mux_port_size == mux_port_id) && (j < op_outsig.size())); - - int op_conn_width = j - op_outsig_offset; - OpMuxConn inp = { - op_outsig.extract(op_outsig_offset, op_conn_width), - mux, - outsig_to_operator.at(op_outsig), - mux_port_id, - mux_port_offset, - op_outsig_offset, - }; - - op_mux_conn_map[op_outsig] = inp; - - --i; - } - }; - - std::function<void(RTLIL::SigSpec)> remove_connected_ops = [&](RTLIL::SigSpec sig) { - auto mux_insig = assign_map(sig); - for (auto outbit : mux_insig) { - if (op_aux_to_outsig.count(outbit)) { - remove_outsig_from_aux_bit(outbit); - continue; - } - - if (!op_outbit_to_outsig.count(outbit)) - continue; - - remove_outsig(op_outbit_to_outsig.at(outbit)); - } - }; - - for (auto cell : module->cells()) { - if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) { - remove_connected_ops(cell->getPort(ID::S)); - find_op_mux_conns(cell); - } else { - for (auto &conn : cell->connections()) - if (cell->input(conn.first)) - remove_connected_ops(conn.second); - } - } - - for (auto w : module->wires()) { - if (!w->port_output) - continue; - - remove_connected_ops(w); - } - - return op_mux_conn_map; -} - struct OptSharePass : public Pass { OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {} void help() override @@ -495,37 +356,46 @@ struct OptSharePass : public Pass { extra_args(args, 1, design); for (auto module : design->selected_modules()) { - assign_map.clear(); - assign_map.set(module); + SigMap sigmap(module); + + dict<RTLIL::SigBit, int> bit_users; + + for (auto cell : module->cells()) + for (auto conn : cell->connections()) + for (auto bit : conn.second) + bit_users[sigmap(bit)]++; + + for (auto wire : module->wires()) + if (wire->port_id != 0) + for (auto bit : SigSpec(wire)) + bit_users[sigmap(bit)]++; std::map<ExtSigSpec, std::set<RTLIL::Cell *>> operand_to_users; - dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator; - dict<RTLIL::SigBit, RTLIL::SigSpec> op_outbit_to_outsig; - dict<RTLIL::SigBit, RTLIL::SigSpec> op_aux_to_outsig; + dict<RTLIL::SigBit, std::pair<RTLIL::Cell *, int>> op_outbit_to_outsig; bool any_shared_operands = false; - std::vector<ExtSigSpec> op_insigs; - for (auto cell : module->cells()) { + for (auto cell : module->selected_cells()) { if (!cell_supported(cell)) continue; + bool skip = false; if (cell->type == ID($alu)) { for (RTLIL::IdString port_name : {ID::X, ID::CO}) { - auto mux_insig = assign_map(cell->getPort(port_name)); - outsig_to_operator[mux_insig] = cell; - for (auto outbit : mux_insig) - op_aux_to_outsig[outbit] = mux_insig; + for (auto outbit : sigmap(cell->getPort(port_name))) + if (bit_users[outbit] > 1) + skip = true; } } - auto mux_insig = assign_map(cell->getPort(ID::Y)); - outsig_to_operator[mux_insig] = cell; - for (auto outbit : mux_insig) - op_outbit_to_outsig[outbit] = mux_insig; + if (skip) + continue; + + auto mux_insig = sigmap(cell->getPort(ID::Y)); + for (int i = 0; i < GetSize(mux_insig); i++) + op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i); for (RTLIL::IdString port_name : {ID::A, ID::B}) { - auto op_insig = decode_port(cell, port_name, &assign_map); - op_insigs.push_back(op_insig); + auto op_insig = decode_port(cell, port_name, sigmap); operand_to_users[op_insig].insert(cell); if (operand_to_users[op_insig].size() > 1) any_shared_operands = true; @@ -537,34 +407,79 @@ struct OptSharePass : public Pass { // Operator outputs need to be exclusively connected to the $mux inputs in order to be mergeable. Hence we count to // how many points are operator output bits connected. - dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map = - find_valid_op_mux_conns(module, op_outbit_to_outsig, outsig_to_operator, op_aux_to_outsig); + std::vector<merged_op_t> merged_ops; - // Group op connections connected to same ports of the same $mux. Sort them in ascending order of their port offset - dict<RTLIL::Cell*, std::vector<std::set<OpMuxConn>>> mux_port_op_conns; - for (auto& val: op_mux_conn_map) { - OpMuxConn p = val.second; - auto& mux_port_conns = mux_port_op_conns[p.mux]; + for (auto mux : module->selected_cells()) { + if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux))) + continue; - if (mux_port_conns.size() == 0) { - int mux_port_num; + int mux_port_size = GetSize(mux->getPort(ID::A)); + int mux_port_num = GetSize(mux->getPort(ID::S)) + 1; - if (p.mux->type.in(ID($mux), ID($_MUX_))) - mux_port_num = 2; - else - mux_port_num = p.mux->getPort(ID::S).size(); + RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)}); + std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num); + int found = 0; - mux_port_conns.resize(mux_port_num); - } + for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) { + SigSpec mux_insig; + if (mux_port_id == mux_port_num - 1) { + mux_insig = sigmap(mux->getPort(ID::A)); + } else { + mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size)); + } - mux_port_conns[p.mux_port_id].insert(p); - } + for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) { + if (!op_outbit_to_outsig.count(mux_insig[mux_port_offset])) + continue; - std::vector<merged_op_t> merged_ops; - for (auto& val: mux_port_op_conns) { + RTLIL::Cell *cell; + int op_outsig_offset; + std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]); + SigSpec op_outsig = sigmap(cell->getPort(ID::Y)); + int op_outsig_size = GetSize(op_outsig); + int op_conn_width = 0; + + while (mux_port_offset + op_conn_width < mux_port_size && + op_outsig_offset + op_conn_width < op_outsig_size && + mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width]) + op_conn_width++; + + log_assert(op_conn_width >= 1); + + bool skip = false; + for (int i = 0; i < op_outsig_size; i++) { + int expected = 1; + if (i >= op_outsig_offset && i < op_outsig_offset + op_conn_width) + expected = 2; + if (bit_users[op_outsig[i]] != expected) + skip = true; + } + if (skip) { + mux_port_offset += op_conn_width; + mux_port_offset--; + continue; + } + + OpMuxConn inp = { + op_outsig.extract(op_outsig_offset, op_conn_width), + mux, + cell, + mux_port_id, + mux_port_offset, + op_outsig_offset, + }; + + mux_port_conns[mux_port_id].insert(inp); + + mux_port_offset += op_conn_width; + mux_port_offset--; - RTLIL::Cell* cell = val.first; - auto &mux_port_conns = val.second; + found++; + } + } + + if (found < 2) + continue; const OpMuxConn *seed = NULL; @@ -612,12 +527,12 @@ struct OptSharePass : public Pass { continue; // Filter mergeable connections whose ops share an operand with seed connection's op - auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users); + auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users, sigmap); if (shared_operand.empty()) continue; - check_muxed_operands(mergeable_conns, shared_operand); + check_muxed_operands(mergeable_conns, shared_operand, sigmap); if (mergeable_conns.size() < 2) continue; @@ -631,7 +546,7 @@ struct OptSharePass : public Pass { seed = NULL; - merged_ops.push_back(merged_op_t{cell, merged_ports, shared_operand}); + merged_ops.push_back(merged_op_t{mux, merged_ports, shared_operand}); design->scratchpad_set_bool("opt.did_something", true); } @@ -647,7 +562,7 @@ struct OptSharePass : public Pass { log(" %s\n", log_id(op.op)); log("\n"); - merge_operators(module, shared.mux, shared.ports, shared.shared_operand); + merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap); } } } |