+OBJS += passes/opt/opt_mem_feedback.o

+OBJS += passes/opt/opt_mem_priority.o

+OBJS += passes/opt/opt_mem_widen.o

+OBJS += passes/opt/opt_dff.o

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");

+ log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n");

+ log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");

+ log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");

+ log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n");

+ log(" while <changed design in opt_dff>\n");

+ std::string opt_dff_args;

+ if (args[argidx] == "-noclkinv") {

+ opt_expr_args += " -noclkinv";

+ opt_dff_args += " -keepdc";

+ continue;

+ }

+ if (args[argidx] == "-nodffe") {

+ opt_dff_args += " -nodffe";

+ continue;

+ }

+ if (args[argidx] == "-nosdff") {

+ opt_dff_args += " -nosdff";

+ opt_dff_args += " -sat";

+ Pass::call(design, "opt_dff" + opt_dff_args);

+ Pass::call(design, "opt_dff" + opt_dff_args);

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/ffinit.h"

+ for (auto wire : module->wires())

+ if (wire->get_bool_attribute(ID::keep)) {

+ found_keep = true;

+ break;

+ }

+ if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))

+ dict<IdString, pool<Cell*>> mem2cells;

+ pool<IdString> mem_unused;

+ FfInitVals ffinit(&sigmap, module);

+ for (auto &it : module->memories) {

+ mem_unused.insert(it.first);

+ }

+

+ for (Cell *cell : module->cells()) {

+ if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {

+ IdString mem_id = cell->getParam(ID::MEMID).decode_string();

+ mem2cells[mem_id].insert(cell);

+ }

+ }

+

+ pool<IdString> mems;

+ for (auto cell : queue) {

+ for (auto &it : cell->connections())

+ if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))

+ for (auto bit : sigmap(it.second))

+ bits.insert(bit);

+

+ if (cell->type.in(ID($memrd), ID($memrd_v2))) {

+ IdString mem_id = cell->getParam(ID::MEMID).decode_string();

+ if (mem_unused.count(mem_id)) {

+ mem_unused.erase(mem_id);

+ mems.insert(mem_id);

+ }

+ }

+ }

+

+

+ for (auto mem : mems)

+ for (auto c : mem2cells[mem])

+ if (unused.count(c))

+ queue.insert(c), unused.erase(c);

+ if (RTLIL::builtin_ff_cell_types().count(cell->type))

+ ffinit.remove_init(cell->getPort(ID::Q));

+ for (auto it : mem_unused)

+ {

+ if (verbose)

+ log_debug(" removing unused memory `%s'.\n", it.c_str());

+ delete module->memories.at(it);

+ module->memories.erase(it);

+ }

+

+ if (w1->name.isPublic() && w2->name.isPublic()) {

+ return w2->name.isPublic();

+ dict<RTLIL::SigBit, RTLIL::State> init_bits;

+ auto it2 = wire->attributes.find(ID::init);

+ if (it2 != wire->attributes.end()) {

+ RTLIL::Const &val = it2->second;

+ SigSpec sig = assign_map(wire);

+ for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)

+ if (val.bits[i] != State::Sx)

+ init_bits[sig[i]] = val.bits[i];

+ wire->attributes.erase(it2);

+ }

+ }

+

+ for (auto wire : module->wires()) {

+ bool found = false;

+ Const val(State::Sx, wire->width);

+ for (int i = 0; i < wire->width; i++) {

+ auto it = init_bits.find(RTLIL::SigBit(wire, i));

+ if (it != init_bits.end()) {

+ val.bits[i] = it->second;

+ found = true;

+ }

+ }

+ if (found)

+ wire->attributes[ID::init] = val;

+ * Copyright (C) 2017 Claire Xenia Wolf <claire@yosyshq.com>

+/*

+ * yosys -- Yosys Open SYnthesis Suite

+ *

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>

+ *

+ * Permission to use, copy, modify, and/or distribute this software for any

+ * purpose with or without fee is hereby granted, provided that the above

+ * copyright notice and this permission notice appear in all copies.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

+ *

+ */

+

+#include "kernel/log.h"

+#include "kernel/register.h"

+#include "kernel/rtlil.h"

+#include "kernel/qcsat.h"

+#include "kernel/modtools.h"

+#include "kernel/sigtools.h"

+#include "kernel/ffinit.h"

+#include "kernel/ff.h"

+#include "passes/techmap/simplemap.h"

+#include <stdio.h>

+#include <stdlib.h>

+

+USING_YOSYS_NAMESPACE

+PRIVATE_NAMESPACE_BEGIN

+

+struct OptDffOptions

+{

+ bool nosdff;

+ bool nodffe;

+ bool simple_dffe;

+ bool sat;

+ bool keepdc;

+};

+

+struct OptDffWorker

+{

+ const OptDffOptions &opt;

+

+ Module *module;

+ typedef std::pair<RTLIL::Cell*, int> cell_int_t;

+ SigMap sigmap;

+ FfInitVals initvals;

+ dict<SigBit, int> bitusers;

+ dict<SigBit, cell_int_t> bit2mux;

+

+ typedef std::map<RTLIL::SigBit, bool> pattern_t;

+ typedef std::set<pattern_t> patterns_t;

+ typedef std::pair<RTLIL::SigBit, bool> ctrl_t;

+ typedef std::set<ctrl_t> ctrls_t;

+

+ // Used as a queue.

+ std::vector<Cell *> dff_cells;

+

+ OptDffWorker(const OptDffOptions &opt, Module *mod) : opt(opt), module(mod), sigmap(mod), initvals(&sigmap, mod) {

+ // Gathering two kinds of information here for every sigmapped SigBit:

+ //

+ // - bitusers: how many users it has (muxes will only be merged into FFs if this is 1, making the FF the only user)

+ // - bit2mux: the mux cell and bit index that drives it, if any

+

+ for (auto wire : module->wires())

+ {

+ if (wire->port_output)

+ for (auto bit : sigmap(wire))

+ bitusers[bit]++;

+ }

+

+ for (auto cell : module->cells()) {

+ if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {

+ RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));

+ for (int i = 0; i < GetSize(sig_y); i++)

+ bit2mux[sig_y[i]] = cell_int_t(cell, i);

+ }

+

+ for (auto conn : cell->connections()) {

+ bool is_output = cell->output(conn.first);

+ if (!is_output || !cell->known()) {

+ for (auto bit : sigmap(conn.second))

+ bitusers[bit]++;

+ }

+ }

+

+ if (module->design->selected(module, cell) && RTLIL::builtin_ff_cell_types().count(cell->type))

+ dff_cells.push_back(cell);

+ }

+

+ }

+

+ State combine_const(State a, State b) {

+ if (a == State::Sx && !opt.keepdc)

+ return b;

+ if (b == State::Sx && !opt.keepdc)

+ return a;

+ if (a == b)

+ return a;

+ return State::Sm;

+ }

+

+ patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)

+ {

+ patterns_t ret;

+

+ if (d == q) {

+ ret.insert(path);

+ return ret;

+ }

+

+ if (bit2mux.count(d) == 0 || bitusers[d] > 1)

+ return ret;

+

+ cell_int_t mbit = bit2mux.at(d);

+ RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A));

+ RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(ID::B));

+ RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S));

+ int width = GetSize(sig_a), index = mbit.second;

+

+ for (int i = 0; i < GetSize(sig_s); i++)

+ if (path.count(sig_s[i]) && path.at(sig_s[i]))

+ {

+ ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);

+

+ if (sig_b[i*width + index] == q) {

+ RTLIL::SigSpec s = mbit.first->getPort(ID::B);

+ s[i*width + index] = RTLIL::Sx;

+ mbit.first->setPort(ID::B, s);

+ }

+

+ return ret;

+ }

+

+ pattern_t path_else = path;

+

+ for (int i = 0; i < GetSize(sig_s); i++)

+ {

+ if (path.count(sig_s[i]))

+ continue;

+

+ pattern_t path_this = path;

+ path_else[sig_s[i]] = false;

+ path_this[sig_s[i]] = true;

+

+ for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this))

+ ret.insert(pat);

+

+ if (sig_b[i*width + index] == q) {

+ RTLIL::SigSpec s = mbit.first->getPort(ID::B);

+ s[i*width + index] = RTLIL::Sx;

+ mbit.first->setPort(ID::B, s);

+ }

+ }

+

+ for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else))

+ ret.insert(pat);

+

+ if (sig_a[index] == q) {

+ RTLIL::SigSpec s = mbit.first->getPort(ID::A);

+ s[index] = RTLIL::Sx;

+ mbit.first->setPort(ID::A, s);

+ }

+

+ return ret;

+ }

+

+ void simplify_patterns(patterns_t&)

+ {

+ // TBD

+ }

+

+ ctrl_t make_patterns_logic(const patterns_t &patterns, const ctrls_t &ctrls, bool make_gates)

+ {

+ if (patterns.empty() && GetSize(ctrls) == 1) {

+ return *ctrls.begin();

+ }

+

+ RTLIL::SigSpec or_input;

+

+ for (auto pat : patterns)

+ {

+ RTLIL::SigSpec s1, s2;

+ for (auto it : pat) {

+ s1.append(it.first);

+ s2.append(it.second);

+ }

+

+ RTLIL::SigSpec y = module->addWire(NEW_ID);

+ RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);

+

+ if (make_gates) {

+ simplemap(module, c);

+ module->remove(c);

+ }

+

+ or_input.append(y);

+ }

+ for (auto item : ctrls) {

+ if (item.second)

+ or_input.append(item.first);

+ else if (make_gates)

+ or_input.append(module->NotGate(NEW_ID, item.first));

+ else

+ or_input.append(module->Not(NEW_ID, item.first));

+ }

+

+ if (GetSize(or_input) == 0)

+ return ctrl_t(State::S1, true);

+

+ if (GetSize(or_input) == 1)

+ return ctrl_t(or_input, true);

+

+ RTLIL::SigSpec y = module->addWire(NEW_ID);

+ RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);

+

+ if (make_gates) {

+ simplemap(module, c);

+ module->remove(c);

+ }

+

+ return ctrl_t(y, true);

+ }

+

+ ctrl_t combine_resets(const ctrls_t &ctrls, bool make_gates)

+ {

+ if (GetSize(ctrls) == 1) {

+ return *ctrls.begin();

+ }

+

+ RTLIL::SigSpec or_input;

+

+ bool final_pol = false;

+ for (auto item : ctrls) {

+ if (item.second)

+ final_pol = true;

+ }

+

+ for (auto item : ctrls) {

+ if (item.second == final_pol)

+ or_input.append(item.first);

+ else if (make_gates)

+ or_input.append(module->NotGate(NEW_ID, item.first));

+ else

+ or_input.append(module->Not(NEW_ID, item.first));

+ }

+

+ RTLIL::SigSpec y = module->addWire(NEW_ID);

+ RTLIL::Cell *c = final_pol ? module->addReduceOr(NEW_ID, or_input, y) : module->addReduceAnd(NEW_ID, or_input, y);

+

+ if (make_gates) {

+ simplemap(module, c);

+ module->remove(c);

+ }

+

+ return ctrl_t(y, final_pol);

+ }

+

+ bool run() {

+ // We have all the information we need, and the list of FFs to process as well. Do it.

+ bool did_something = false;

+ while (!dff_cells.empty()) {

+ Cell *cell = dff_cells.back();

+ dff_cells.pop_back();

+ // Break down the FF into pieces.

+ FfData ff(&initvals, cell);

+ bool changed = false;

+

+ if (!ff.width) {

+ ff.remove();

+ did_something = true;

+ continue;

+ }

+

+ if (ff.has_sr) {

+ bool sr_removed = false;

+ std::vector<int> keep_bits;

+ // Check for always-active S/R bits.

+ for (int i = 0; i < ff.width; i++) {

+ if (ff.sig_clr[i] == (ff.pol_clr ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_clr[i] == State::Sx)) {

+ // Always-active clear — connect Q bit to 0.

+ initvals.remove_init(ff.sig_q[i]);

+ module->connect(ff.sig_q[i], State::S0);

+ log("Handling always-active CLR at position %d on %s (%s) from module %s (changing to const driver).\n",

+ i, log_id(cell), log_id(cell->type), log_id(module));

+ sr_removed = true;

+ } else if (ff.sig_set[i] == (ff.pol_set ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_set[i] == State::Sx)) {

+ // Always-active set — connect Q bit to 1 if clear inactive, 0 if reset active.

+ initvals.remove_init(ff.sig_q[i]);

+ if (!ff.pol_clr) {

+ module->connect(ff.sig_q[i], ff.sig_clr[i]);

+ } else if (ff.is_fine) {

+ module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);

+ } else {

+ module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);

+ }

+ log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",

+ i, log_id(cell), log_id(cell->type), log_id(module));

+ sr_removed = true;

+ } else {

+ keep_bits.push_back(i);

+ }

+ }

+ if (sr_removed) {

+ if (keep_bits.empty()) {

+ module->remove(cell);

+ did_something = true;

+ continue;

+ }

+ ff = ff.slice(keep_bits);

+ ff.cell = cell;

+ changed = true;

+ }

+

+ if (ff.pol_clr ? ff.sig_clr.is_fully_zero() : ff.sig_clr.is_fully_ones()) {

+ // CLR is useless, try to kill it.

+ bool failed = false;

+ for (int i = 0; i < ff.width; i++)

+ if (ff.sig_set[i] != ff.sig_set[0])

+ failed = true;

+ if (!failed) {

+ log("Removing never-active CLR on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_sr = false;

+ ff.has_arst = true;

+ ff.pol_arst = ff.pol_set;

+ ff.sig_arst = ff.sig_set[0];

+ ff.val_arst = Const(State::S1, ff.width);

+ changed = true;

+ }

+ } else if (ff.pol_set ? ff.sig_set.is_fully_zero() : ff.sig_set.is_fully_ones()) {

+ // SET is useless, try to kill it.

+ bool failed = false;

+ for (int i = 0; i < ff.width; i++)

+ if (ff.sig_clr[i] != ff.sig_clr[0])

+ failed = true;

+ if (!failed) {

+ log("Removing never-active SET on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_sr = false;

+ ff.has_arst = true;

+ ff.pol_arst = ff.pol_clr;

+ ff.sig_arst = ff.sig_clr[0];

+ ff.val_arst = Const(State::S0, ff.width);

+ changed = true;

+ }

+ } else if (ff.pol_clr == ff.pol_set) {

+ // Try a more complex conversion to plain async reset.

+ State val_neutral = ff.pol_set ? State::S0 : State::S1;

+ Const val_arst;

+ SigSpec sig_arst;

+ if (ff.sig_clr[0] == val_neutral)

+ sig_arst = ff.sig_set[0];

+ else

+ sig_arst = ff.sig_clr[0];

+ bool failed = false;

+ for (int i = 0; i < ff.width; i++) {

+ if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)

+ val_arst.bits.push_back(State::S0);

+ else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)

+ val_arst.bits.push_back(State::S1);

+ else

+ failed = true;

+ }

+ if (!failed) {

+ log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_sr = false;

+ ff.has_arst = true;

+ ff.val_arst = val_arst;

+ ff.sig_arst = sig_arst;

+ ff.pol_arst = ff.pol_clr;

+ changed = true;

+ }

+ }

+ }

+

+ if (ff.has_aload) {

+ if (ff.sig_aload == (ff.pol_aload ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_aload == State::Sx)) {

+ // Always-inactive enable — remove.

+ log("Removing never-active async load on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_aload = false;

+ changed = true;

+ } else if (ff.sig_aload == (ff.pol_aload ? State::S1 : State::S0)) {

+ // Always-active enable. Make a comb circuit, nuke the FF/latch.

+ log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.remove();

+ if (ff.has_sr) {

+ SigSpec tmp;

+ if (ff.is_fine) {

+ if (ff.pol_set)

+ tmp = module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set);

+ else

+ tmp = module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);

+ if (ff.pol_clr)

+ module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);

+ else

+ module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);

+ } else {

+ if (ff.pol_set)

+ tmp = module->Or(NEW_ID, ff.sig_ad, ff.sig_set);

+ else

+ tmp = module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));

+ if (ff.pol_clr)

+ module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);

+ else

+ module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);

+ }

+ } else if (ff.has_arst) {

+ if (ff.is_fine) {

+ if (ff.pol_arst)

+ module->addMuxGate(NEW_ID, ff.sig_ad, ff.val_arst[0], ff.sig_arst, ff.sig_q);

+ else

+ module->addMuxGate(NEW_ID, ff.val_arst[0], ff.sig_ad, ff.sig_arst, ff.sig_q);

+ } else {

+ if (ff.pol_arst)

+ module->addMux(NEW_ID, ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q);

+ else

+ module->addMux(NEW_ID, ff.val_arst, ff.sig_ad, ff.sig_arst, ff.sig_q);

+ }

+ } else {

+ module->connect(ff.sig_q, ff.sig_ad);

+ }

+ did_something = true;

+ continue;

+ } else if (ff.sig_ad.is_fully_const() && !ff.has_arst && !ff.has_sr) {

+ log("Changing const-value async load to async reset on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_arst = true;

+ ff.has_aload = false;

+ ff.sig_arst = ff.sig_aload;

+ ff.pol_arst = ff.pol_aload;

+ ff.val_arst = ff.sig_ad.as_const();

+ changed = true;

+ }

+ }

+

+ if (ff.has_arst) {

+ if (ff.sig_arst == (ff.pol_arst ? State::S0 : State::S1)) {

+ // Always-inactive reset — remove.

+ log("Removing never-active ARST on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_arst = false;

+ changed = true;

+ } else if (ff.sig_arst == (ff.pol_arst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_arst == State::Sx)) {

+ // Always-active async reset — change to const driver.

+ log("Handling always-active ARST on %s (%s) from module %s (changing to const driver).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.remove();

+ module->connect(ff.sig_q, ff.val_arst);

+ did_something = true;

+ continue;

+ }

+ }

+

+ if (ff.has_srst) {

+ if (ff.sig_srst == (ff.pol_srst ? State::S0 : State::S1)) {

+ // Always-inactive reset — remove.

+ log("Removing never-active SRST on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_srst = false;

+ changed = true;

+ } else if (ff.sig_srst == (ff.pol_srst ? State::S1 : State::S0) || (!opt.keepdc && ff.sig_srst == State::Sx)) {

+ // Always-active sync reset — connect to D instead.

+ log("Handling always-active SRST on %s (%s) from module %s (changing to const D).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_srst = false;

+ if (!ff.ce_over_srst)

+ ff.has_ce = false;

+ ff.sig_d = ff.val_srst;

+ changed = true;

+ }

+ }

+

+ if (ff.has_ce) {

+ if (ff.sig_ce == (ff.pol_ce ? State::S0 : State::S1) || (!opt.keepdc && ff.sig_ce == State::Sx)) {

+ // Always-inactive enable — remove.

+ if (ff.has_srst && !ff.ce_over_srst) {

+ log("Handling never-active EN on %s (%s) from module %s (connecting SRST instead).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ // FF with sync reset — connect the sync reset to D instead.

+ ff.pol_ce = ff.pol_srst;

+ ff.sig_ce = ff.sig_srst;

+ ff.has_srst = false;

+ ff.sig_d = ff.val_srst;

+ changed = true;

+ } else {

+ log("Handling never-active EN on %s (%s) from module %s (removing D path).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ // The D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).

+ ff.has_ce = ff.has_clk = ff.has_srst = false;

+ changed = true;

+ }

+ } else if (ff.sig_ce == (ff.pol_ce ? State::S1 : State::S0)) {

+ // Always-active enable. Just remove it.

+ // For FF, just remove the useless enable.

+ log("Removing always-active EN on %s (%s) from module %s.\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_ce = false;

+ changed = true;

+ }

+ }

+

+ if (ff.has_clk) {

+ if (ff.sig_clk.is_fully_const()) {

+ // Const clock — the D input path is effectively useless, so remove it (this will be a D latch, SR latch, or a const driver).

+ log("Handling const CLK on %s (%s) from module %s (removing D path).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_ce = ff.has_clk = ff.has_srst = false;

+ changed = true;

+ }

+ }

+

+ if ((ff.has_clk || ff.has_gclk) && ff.sig_d == ff.sig_q) {

+ // Q wrapped back to D, can be removed.

+ if (ff.has_clk && ff.has_srst) {

+ // FF with sync reset — connect the sync reset to D instead.

+ log("Handling D = Q on %s (%s) from module %s (conecting SRST instead).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ if (ff.has_ce && ff.ce_over_srst) {

+ if (!ff.pol_ce) {

+ if (ff.is_fine)

+ ff.sig_ce = module->NotGate(NEW_ID, ff.sig_ce);

+ else

+ ff.sig_ce = module->Not(NEW_ID, ff.sig_ce);

+ }

+ if (!ff.pol_srst) {

+ if (ff.is_fine)

+ ff.sig_srst = module->NotGate(NEW_ID, ff.sig_srst);

+ else

+ ff.sig_srst = module->Not(NEW_ID, ff.sig_srst);

+ }

+ if (ff.is_fine)

+ ff.sig_ce = module->AndGate(NEW_ID, ff.sig_ce, ff.sig_srst);

+ else

+ ff.sig_ce = module->And(NEW_ID, ff.sig_ce, ff.sig_srst);

+ ff.pol_ce = true;

+ } else {

+ ff.pol_ce = ff.pol_srst;

+ ff.sig_ce = ff.sig_srst;

+ }

+ ff.has_ce = true;

+ ff.has_srst = false;

+ ff.sig_d = ff.val_srst;

+ changed = true;

+ } else {

+ // The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).

+ log("Handling D = Q on %s (%s) from module %s (removing D path).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_clk = ff.has_ce = false;

+ changed = true;

+ }

+ }

+

+ if (ff.has_aload && !ff.has_clk && ff.sig_ad == ff.sig_q) {

+ log("Handling AD = Q on %s (%s) from module %s (removing async load path).\n",

+ log_id(cell), log_id(cell->type), log_id(module));

+ ff.has_aload = false;

+ changed = true;

+ }

+

+ // The cell has been simplified as much as possible already. Now try to spice it up with enables / sync resets.

+ if (ff.has_clk) {

+ if (!ff.has_arst && !ff.has_sr && (!ff.has_srst || !ff.has_ce || ff.ce_over_srst) && !opt.nosdff) {

+ // Try to merge sync resets.

+ std::map<ctrls_t, std::vector<int>> groups;

+ std::vector<int> remaining_indices;

+ Const val_srst;

+

+ for (int i = 0 ; i < ff.width; i++) {

+ ctrls_t resets;

+ State reset_val = State::Sx;

+ if (ff.has_srst)

+ reset_val = ff.val_srst[i];

+ while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {

+ cell_int_t mbit = bit2mux.at(ff.sig_d[i]);

+ if (GetSize(mbit.first->getPort(ID::S)) != 1)

+ break;

+ SigBit s = mbit.first->getPort(ID::S);

+ SigBit a = mbit.first->getPort(ID::A)[mbit.second];

+ SigBit b = mbit.first->getPort(ID::B)[mbit.second];

+ // Workaround for funny memory WE pattern.

+ if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))

+ break;

+ if ((b == State::S0 || b == State::S1) && (b == reset_val || reset_val == State::Sx)) {

+ // This is better handled by CE pattern.

+ if (a == ff.sig_q[i])

+ break;

+ reset_val = b.data;

+ resets.insert(ctrl_t(s, true));

+ ff.sig_d[i] = a;

+ } else if ((a == State::S0 || a == State::S1) && (a == reset_val || reset_val == State::Sx)) {

+ // This is better handled by CE pattern.

+ if (b == ff.sig_q[i])

+ break;

+ reset_val = a.data;

+ resets.insert(ctrl_t(s, false));

+ ff.sig_d[i] = b;

+ } else {

+ break;

+ }

+ }

+

+ if (!resets.empty()) {

+ if (ff.has_srst)

+ resets.insert(ctrl_t(ff.sig_srst, ff.pol_srst));

+ groups[resets].push_back(i);

+ } else

+ remaining_indices.push_back(i);

+ val_srst.bits.push_back(reset_val);

+ }

+

+ for (auto &it : groups) {

+ FfData new_ff = ff.slice(it.second);

+ new_ff.val_srst = Const();

+ for (int i = 0; i < new_ff.width; i++) {

+ int j = it.second[i];

+ new_ff.val_srst.bits.push_back(val_srst[j]);

+ }

+ ctrl_t srst = combine_resets(it.first, ff.is_fine);

+

+ new_ff.has_srst = true;

+ new_ff.sig_srst = srst.first;

+ new_ff.pol_srst = srst.second;

+ if (new_ff.has_ce)

+ new_ff.ce_over_srst = true;

+ Cell *new_cell = new_ff.emit();

+ if (new_cell)

+ dff_cells.push_back(new_cell);

+ log("Adding SRST signal on %s (%s) from module %s (D = %s, Q = %s, rval = %s).\n",

+ log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q), log_signal(new_ff.val_srst));

+ }

+

+ if (remaining_indices.empty()) {

+ module->remove(cell);

+ did_something = true;

+ continue;

+ } else if (GetSize(remaining_indices) != ff.width) {

+ ff = ff.slice(remaining_indices);

+ ff.cell = cell;

+ changed = true;

+ }

+ }

+ if ((!ff.has_srst || !ff.has_ce || !ff.ce_over_srst) && !opt.nodffe) {

+ // Try to merge enables.

+ std::map<std::pair<patterns_t, ctrls_t>, std::vector<int>> groups;

+ std::vector<int> remaining_indices;

+

+ for (int i = 0 ; i < ff.width; i++) {

+ // First, eat up as many simple muxes as possible.

+ ctrls_t enables;

+ while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {

+ cell_int_t mbit = bit2mux.at(ff.sig_d[i]);

+ if (GetSize(mbit.first->getPort(ID::S)) != 1)

+ break;

+ SigBit s = mbit.first->getPort(ID::S);

+ SigBit a = mbit.first->getPort(ID::A)[mbit.second];

+ SigBit b = mbit.first->getPort(ID::B)[mbit.second];

+ if (a == ff.sig_q[i]) {

+ enables.insert(ctrl_t(s, true));

+ ff.sig_d[i] = b;

+ } else if (b == ff.sig_q[i]) {

+ enables.insert(ctrl_t(s, false));

+ ff.sig_d[i] = a;

+ } else {

+ break;

+ }

+ }

+

+ patterns_t patterns;

+ if (!opt.simple_dffe)

+ patterns = find_muxtree_feedback_patterns(ff.sig_d[i], ff.sig_q[i], pattern_t());

+ if (!patterns.empty() || !enables.empty()) {

+ if (ff.has_ce)

+ enables.insert(ctrl_t(ff.sig_ce, ff.pol_ce));

+ simplify_patterns(patterns);

+ groups[std::make_pair(patterns, enables)].push_back(i);

+ } else

+ remaining_indices.push_back(i);

+ }

+

+ for (auto &it : groups) {

+ FfData new_ff = ff.slice(it.second);

+ ctrl_t en = make_patterns_logic(it.first.first, it.first.second, ff.is_fine);

+

+ new_ff.has_ce = true;

+ new_ff.sig_ce = en.first;

+ new_ff.pol_ce = en.second;

+ new_ff.ce_over_srst = false;

+ Cell *new_cell = new_ff.emit();

+ if (new_cell)

+ dff_cells.push_back(new_cell);

+ log("Adding EN signal on %s (%s) from module %s (D = %s, Q = %s).\n",

+ log_id(cell), log_id(cell->type), log_id(module), log_signal(new_ff.sig_d), log_signal(new_ff.sig_q));

+ }

+

+ if (remaining_indices.empty()) {

+ module->remove(cell);

+ did_something = true;

+ continue;

+ } else if (GetSize(remaining_indices) != ff.width) {

+ ff = ff.slice(remaining_indices);

+ ff.cell = cell;

+ changed = true;

+ }

+ }

+ }

+

+ if (changed) {

+ // Rebuild the FF.

+ ff.emit();

+ did_something = true;

+ }

+ }

+ return did_something;

+ }

+

+ bool run_constbits() {

+ ModWalker modwalker(module->design, module);

+ QuickConeSat qcsat(modwalker);

+

+ // Run as a separate sub-pass, so that we don't mutate (non-FF) cells under ModWalker.

+ bool did_something = false;

+ for (auto cell : module->selected_cells()) {

+ if (!RTLIL::builtin_ff_cell_types().count(cell->type))

+ continue;

+ FfData ff(&initvals, cell);

+

+ // Now check if any bit can be replaced by a constant.

+ pool<int> removed_sigbits;

+ for (int i = 0; i < ff.width; i++) {

+ State val = ff.val_init[i];

+ if (ff.has_arst)

+ val = combine_const(val, ff.val_arst[i]);

+ if (ff.has_srst)

+ val = combine_const(val, ff.val_srst[i]);

+ if (ff.has_sr) {

+ if (ff.sig_clr[i] != (ff.pol_clr ? State::S0 : State::S1))

+ val = combine_const(val, State::S0);

+ if (ff.sig_set[i] != (ff.pol_set ? State::S0 : State::S1))

+ val = combine_const(val, State::S1);

+ }

+ if (val == State::Sm)

+ continue;

+ if (ff.has_clk || ff.has_gclk) {

+ if (!ff.sig_d[i].wire) {

+ val = combine_const(val, ff.sig_d[i].data);

+ if (val == State::Sm)

+ continue;

+ } else {

+ if (!opt.sat)

+ continue;

+ // For each register bit, try to prove that it cannot change from the initial value. If so, remove it

+ if (!modwalker.has_drivers(ff.sig_d.extract(i)))

+ continue;

+ if (val != State::S0 && val != State::S1)

+ continue;

+

+ int init_sat_pi = qcsat.importSigBit(val);

+ int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]);

+ int d_sat_pi = qcsat.importSigBit(ff.sig_d[i]);

+

+ qcsat.prepare();

+

+ // Try to find out whether the register bit can change under some circumstances

+ bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));

+

+ // If the register bit cannot change, we can replace it with a constant

+ if (counter_example_found)

+ continue;

+ }

+ }

+ if (ff.has_aload) {

+ if (!ff.sig_ad[i].wire) {

+ val = combine_const(val, ff.sig_ad[i].data);

+ if (val == State::Sm)

+ continue;

+ } else {

+ if (!opt.sat)

+ continue;

+ // For each register bit, try to prove that it cannot change from the initial value. If so, remove it

+ if (!modwalker.has_drivers(ff.sig_ad.extract(i)))

+ continue;

+ if (val != State::S0 && val != State::S1)

+ continue;

+

+ int init_sat_pi = qcsat.importSigBit(val);

+ int q_sat_pi = qcsat.importSigBit(ff.sig_q[i]);

+ int d_sat_pi = qcsat.importSigBit(ff.sig_ad[i]);

+

+ qcsat.prepare();

+

+ // Try to find out whether the register bit can change under some circumstances

+ bool counter_example_found = qcsat.ez->solve(qcsat.ez->IFF(q_sat_pi, init_sat_pi), qcsat.ez->NOT(qcsat.ez->IFF(d_sat_pi, init_sat_pi)));

+

+ // If the register bit cannot change, we can replace it with a constant

+ if (counter_example_found)

+ continue;

+ }

+ }

+ log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", val ? 1 : 0,

+ i, log_id(cell), log_id(cell->type), log_id(module));

+

+ initvals.remove_init(ff.sig_q[i]);

+ module->connect(ff.sig_q[i], val);

+ removed_sigbits.insert(i);

+ }

+ if (!removed_sigbits.empty()) {

+ std::vector<int> keep_bits;

+ for (int i = 0; i < ff.width; i++)

+ if (!removed_sigbits.count(i))

+ keep_bits.push_back(i);

+ if (keep_bits.empty()) {

+ module->remove(cell);

+ did_something = true;

+ continue;

+ }

+ ff = ff.slice(keep_bits);

+ ff.cell = cell;

+ ff.emit();

+ did_something = true;

+ }

+ }

+ return did_something;

+ }

+};

+

+struct OptDffPass : public Pass {

+ OptDffPass() : Pass("opt_dff", "perform DFF optimizations") { }

+ void help() override

+ {

+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

+ log("\n");

+ log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] [selection]\n");

+ log("\n");

+ log("This pass converts flip-flops to a more suitable type by merging clock enables\n");

+ log("and synchronous reset multiplexers, removing unused control inputs, or potentially\n");

+ log("removes the flip-flop altogether, converting it to a constant driver.\n");

+ log("\n");

+ log(" -nodffe\n");

+ log(" disables dff -> dffe conversion, and other transforms recognizing clock enable\n");

+ log("\n");

+ log(" -nosdff\n");

+ log(" disables dff -> sdff conversion, and other transforms recognizing sync resets\n");

+ log("\n");

+ log(" -simple-dffe\n");

+ log(" only enables clock enable recognition transform for obvious cases\n");

+ log("\n");

+ log(" -sat\n");

+ log(" additionally invoke SAT solver to detect and remove flip-flops (with\n");

+ log(" non-constant inputs) that can also be replaced with a constant driver\n");

+ log("\n");

+ log(" -keepdc\n");

+ log(" some optimizations change the behavior of the circuit with respect to\n");

+ log(" don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause\n");

+ log(" all result bits to be set to x. this behavior changes when 'a+0' is\n");

+ log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n");

+ log("\n");

+ }

+

+ void execute(std::vector<std::string> args, RTLIL::Design *design) override

+ {

+ log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n");

+ OptDffOptions opt;

+ opt.nodffe = false;

+ opt.nosdff = false;

+ opt.simple_dffe = false;

+ opt.keepdc = false;

+ opt.sat = false;

+

+ size_t argidx;

+ for (argidx = 1; argidx < args.size(); argidx++) {

+ if (args[argidx] == "-nodffe") {

+ opt.nodffe = true;

+ continue;

+ }

+ if (args[argidx] == "-nosdff") {

+ opt.nosdff = true;

+ continue;

+ }

+ if (args[argidx] == "-simple-dffe") {

+ opt.simple_dffe = true;

+ continue;

+ }

+ if (args[argidx] == "-keepdc") {

+ opt.keepdc = true;

+ continue;

+ }

+ if (args[argidx] == "-sat") {

+ opt.sat = true;

+ continue;

+ }

+ break;

+ }

+ extra_args(args, argidx, design);

+

+ bool did_something = false;

+ for (auto mod : design->selected_modules()) {

+ OptDffWorker worker(opt, mod);

+ if (worker.run())

+ did_something = true;

+ if (worker.run_constbits())

+ did_something = true;

+ }

+

+ if (did_something)

+ design->scratchpad_set_bool("opt.did_something", true);

+ }

+} OptDffPass;

+

+PRIVATE_NAMESPACE_END

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)

+ if (!noclkinv)

+ if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))

+ if (cell->type.in(ID($aldff), ID($aldffe)))

+ handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);

+

+ if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))

+ handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);

+ handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);

+

+ handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);

+ handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);

+ handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);

+

+ int width = GetSize(cell->getPort(ID::Y));

+ if (sig_b.is_fully_const())

+ if (sig_a.is_fully_def())

+ if (sig_a.is_fully_zero())

+ int exp;

+ if (sig_a.is_onehot(&exp) && !(a_signed && exp == GetSize(sig_a) - 1))

+ {

+ if (swapped_ab)

+ cover("opt.opt_expr.mul_shift.swapped");

+ else

+ cover("opt.opt_expr.mul_shift.unswapped");

+ log_debug("Replacing multiply-by-%s cell `%s' in module `%s' with shift-by-%d.\n",

+ log_signal(sig_a), cell->name.c_str(), module->name.c_str(), exp);

+ if (!swapped_ab) {

+ cell->setPort(ID::A, cell->getPort(ID::B));

+ cell->parameters.at(ID::A_WIDTH) = cell->parameters.at(ID::B_WIDTH);

+ cell->parameters.at(ID::A_SIGNED) = cell->parameters.at(ID::B_SIGNED);

+ }

+ Const new_b = exp;

+ cell->type = ID($shl);

+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);

+ cell->parameters[ID::B_SIGNED] = false;

+ cell->setPort(ID::B, new_b);

+ cell->check();

+ did_something = true;

+ goto next_cell;

+ }

+ if (y_zeros >= GetSize(sig_y)) {

+ module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y)));

+ module->remove(cell);

+

+ did_something = true;

+ goto next_cell;

+ }

+

+ if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))

+ if (sig_b.is_fully_def())

+ if (sig_b.is_fully_zero())

+ int exp;

+ if (!keepdc && sig_b.is_onehot(&exp) && !(b_signed && exp == GetSize(sig_b) - 1))

+ {

+ if (cell->type.in(ID($div), ID($divfloor)))

+ cover("opt.opt_expr.div_shift");

+ bool is_truncating = cell->type == ID($div);

+ log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n",

+ is_truncating ? "truncating" : "flooring",

+ log_signal(sig_b), cell->name.c_str(), module->name.c_str(), exp);

+ Const new_b = exp;

+ cell->type = ID($sshr);

+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);

+ cell->parameters[ID::B_SIGNED] = false;

+ cell->setPort(ID::B, new_b);

+ // Truncating division is the same as flooring division, except when

+ // the result is negative and there is a remainder - then trunc = floor + 1

+ if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {

+ Wire *flooring = module->addWire(NEW_ID, sig_y.size());

+ cell->setPort(ID::Y, flooring);

+ SigSpec a_sign = sig_a[sig_a.size()-1];

+ SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));

+ SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);

+ module->addAdd(NEW_ID, flooring, should_add, sig_y);

+

+ cell->check();

+ }

+ else if (cell->type.in(ID($mod), ID($modfloor)))

+ {

+ cover("opt.opt_expr.mod_mask");

+

+ bool is_truncating = cell->type == ID($mod);

+ log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n",

+ is_truncating ? "truncating" : "flooring",

+ log_signal(sig_b), cell->name.c_str(), module->name.c_str());

+

+ // truncating modulo has the same masked bits as flooring modulo, but

+ // the sign bits are those of A (except when R=0)

+ if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0)

+ module->remove(cell);

+ SigSpec truncating = sig_a.extract(0, exp);

+ SigSpec a_sign = sig_a[sig_a.size()-1];

+ SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));

+ SigSpec extend_bit = module->And(NEW_ID, a_sign, rem_nonzero);

+ truncating.append(extend_bit);

+ module->addPos(NEW_ID, truncating, sig_y, true);

+ }

+ else

+ {

+ std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(State::S1, exp);

+ if (b_signed || exp == 0)

+

+ did_something = true;

+ goto next_cell;

+ }

+ int const_bit_hot;

+ if (const_sig.is_onehot(&const_bit_hot) && const_bit_hot < var_width)

+void replace_const_connections(RTLIL::Module *module) {

+ SigMap assign_map(module);

+ for (auto cell : module->selected_cells())

+ {

+ std::vector<std::pair<RTLIL::IdString, SigSpec>> changes;

+ for (auto &conn : cell->connections()) {

+ SigSpec mapped = assign_map(conn.second);

+ if (conn.second != mapped && mapped.is_fully_const())

+ changes.push_back({conn.first, mapped});

+ }

+ if (!changes.empty())

+ did_something = true;

+ for (auto &it : changes)

+ cell->setPort(it.first, it.second);

+ }

+}

+

+ log(" -noclkinv\n");

+ log(" do not optimize clock inverters by changing FF types\n");

+ bool noclkinv = false;

+ if (args[argidx] == "-noclkinv") {

+ noclkinv = true;

+ replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);

+ replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);

+ did_something = false;

+ replace_const_connections(module);

+ if (did_something)

+ design->scratchpad_set_bool("opt.did_something", true);

+

+struct dlogic_t {

+ IdString cell_type;

+ // LUT input idx -> hard cell's port name

+ dict<int, IdString> lut_input_port;

+};

+

+ const std::vector<dlogic_t> &dlogic;

+ dict<RTLIL::Cell*, pool<std::pair<int, RTLIL::Cell*>>> luts_dlogics;

+ std::vector<int> dlogic_counts(dlogic.size());

+ dlogic_counts[lut_dlogic.first]++;

+ for (int i = 0; i < GetSize(dlogic); i++)

+ log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]);

+ OptLutWorker(const std::vector<dlogic_t> &dlogic, RTLIL::Module *module, int limit) :

+ pool<std::pair<int, RTLIL::Cell*>> lut_all_dlogics;

+ for (int j = 0; j < GetSize(dlogic); j++)

+ if (dlogic[j].cell_type == port.cell->type)

+ if (port.port == dlogic[j].lut_input_port.at(i, IdString()))

+ lut_all_dlogics.insert({j, port.cell});

+ pool<std::pair<int, RTLIL::Cell*>> lut_legal_dlogics;

+ auto &dlogic_map = dlogic[lut_dlogic.first].lut_input_port;

+ log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));

+ if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)))

+ log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));

+ log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second)));

+ log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second));

+ module->remove(lut);

+

+ lutR->module->remove(lutR);

+

+ std::vector<dlogic_t> dlogic;

+ dlogic_t entry;

+ entry.cell_type = "\\" + tokens[0];

+ entry.lut_input_port[lut_input] = logic_port;

+ dlogic.push_back(entry);

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ if (techname == "gowin") {

+ // Pad the LUT to 1 input, adding consts from the front.

+ if (new_inputs.empty()) {

+ new_inputs.insert(new_inputs.begin(), State::S0);

+ }

+ }

+ // For ecp5, and gowin do not replace with a const driver — the nextpnr

+ if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/mem.h"

+ SigMap sigmap(module);

+ FfInitVals initvals(&sigmap, module);

+ for (auto &mem : Mem::get_selected_memories(module)) {

+ bool changed = false;

+ for (auto &port : mem.wr_ports) {

+ if (port.en.is_fully_zero()) {

+ port.removed = true;

+ changed = true;

+ total_count++;

+ }

+ }

+ if (changed) {

+ mem.emit();

+ }

+

+ if (mem.wr_ports.empty() && mem.inits.empty()) {

+ // The whole memory array will contain

+ // only State::Sx, but the embedded read

+ // registers could have reset or init values.

+ // They will probably be optimized away by

+ // opt_dff later.

+ for (int i = 0; i < GetSize(mem.rd_ports); i++) {

+ mem.extract_rdff(i, &initvals);

+ auto &port = mem.rd_ports[i];

+ module->connect(port.data, Const(State::Sx, GetSize(port.data)));

+ }

+ mem.remove();

+ total_count++;

+ }

+/*

+ * yosys -- Yosys Open SYnthesis Suite

+ *

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ *

+ * Permission to use, copy, modify, and/or distribute this software for any

+ * purpose with or without fee is hereby granted, provided that the above

+ * copyright notice and this permission notice appear in all copies.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

+ *

+ */

+

+#include "kernel/yosys.h"

+#include "kernel/sigtools.h"

+#include "kernel/mem.h"

+

+USING_YOSYS_NAMESPACE

+PRIVATE_NAMESPACE_BEGIN

+

+// Describes found feedback path.

+struct FeedbackPath {

+ // Which write port it is.

+ int wrport_idx;

+ // Which data bit of that write port it is.

+ int data_bit_idx;

+ // Values of all mux select signals that need to be set to select this path.

+ dict<RTLIL::SigBit, bool> condition;

+ // The exact feedback bit used (used to match read port).

+ SigBit feedback_bit;

+

+ FeedbackPath(int wrport_idx, int data_bit_idx, dict<RTLIL::SigBit, bool> condition, SigBit feedback_bit) : wrport_idx(wrport_idx), data_bit_idx(data_bit_idx), condition(condition), feedback_bit(feedback_bit) {}

+};

+

+struct OptMemFeedbackWorker

+{

+ RTLIL::Design *design;

+ RTLIL::Module *module;

+ SigMap sigmap, sigmap_xmux;

+ FfInitVals initvals;

+

+ dict<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;

+ dict<RTLIL::SigBit, int> sig_users_count;

+ dict<pair<pool<dict<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;

+

+

+ // -----------------------------------------------------------------

+ // Converting feedbacks to async read ports to proper enable signals

+ // -----------------------------------------------------------------

+

+ void find_data_feedback(const pool<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig,

+ const dict<RTLIL::SigBit, bool> &state,

+ int wrport_idx, int data_bit_idx,

+ std::vector<FeedbackPath> &paths)

+ {

+ if (async_rd_bits.count(sig)) {

+ paths.push_back(FeedbackPath(wrport_idx, data_bit_idx, state, sig));

+ return;

+ }

+

+ if (sig_users_count[sig] != 1) {

+ // Only descend into muxes if we're the only user.

+ return;

+ }

+

+ if (sig_to_mux.count(sig) == 0)

+ return;

+

+ RTLIL::Cell *cell = sig_to_mux.at(sig).first;

+ int bit_idx = sig_to_mux.at(sig).second;

+

+ std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));

+ std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));

+ std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));

+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));

+ log_assert(sig_y.at(bit_idx) == sig);

+

+ for (int i = 0; i < GetSize(sig_s); i++)

+ if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {

+ find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, wrport_idx, data_bit_idx, paths);

+ return;

+ }

+

+

+ for (int i = 0; i < GetSize(sig_s); i++)

+ {

+ if (state.count(sig_s[i]) && state.at(sig_s[i]) == false)

+ continue;

+

+ dict<RTLIL::SigBit, bool> new_state = state;

+ new_state[sig_s[i]] = true;

+

+ find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, wrport_idx, data_bit_idx, paths);

+ }

+

+ dict<RTLIL::SigBit, bool> new_state = state;

+ for (auto bit : sig_s)

+ new_state[bit] = false;

+

+ find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, wrport_idx, data_bit_idx, paths);

+ }

+

+ RTLIL::SigBit conditions_to_logic(pool<dict<RTLIL::SigBit, bool>> &conditions, SigBit olden)

+ {

+ auto key = make_pair(conditions, olden);

+

+ if (conditions_logic_cache.count(key))

+ return conditions_logic_cache.at(key);

+

+ RTLIL::SigSpec terms;

+ for (auto &cond : conditions) {

+ RTLIL::SigSpec sig1, sig2;

+ for (auto &it : cond) {

+ sig1.append(it.first);

+ sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);

+ }

+ terms.append(module->Ne(NEW_ID, sig1, sig2));

+ }

+

+ if (olden != State::S1)

+ terms.append(olden);

+

+ if (GetSize(terms) == 0)

+ terms = State::S1;

+

+ if (GetSize(terms) > 1)

+ terms = module->ReduceAnd(NEW_ID, terms);

+

+ return conditions_logic_cache[key] = terms;

+ }

+

+ void translate_rd_feedback_to_en(Mem &mem)

+ {

+ // Look for async read ports that may be suitable for feedback paths.

+ dict<RTLIL::SigSpec, std::vector<pool<RTLIL::SigBit>>> async_rd_bits;

+

+ for (auto &port : mem.rd_ports)

+ {

+ if (port.clk_enable)

+ continue;

+

+ for (int sub = 0; sub < (1 << port.wide_log2); sub++) {

+ SigSpec addr = sigmap_xmux(port.sub_addr(sub));

+ async_rd_bits[addr].resize(mem.width);

+ for (int i = 0; i < mem.width; i++)

+ async_rd_bits[addr][i].insert(sigmap(port.data[i + sub * mem.width]));

+ }

+ }

+

+ if (async_rd_bits.empty())

+ return;

+

+ // Look for actual feedback paths.

+ std::vector<FeedbackPath> paths;

+

+ for (int i = 0; i < GetSize(mem.wr_ports); i++)

+ {

+ auto &port = mem.wr_ports[i];

+

+ log(" Analyzing %s.%s write port %d.\n", log_id(module), log_id(mem.memid), i);

+

+ for (int sub = 0; sub < (1 << port.wide_log2); sub++)

+ {

+ SigSpec addr = sigmap_xmux(port.sub_addr(sub));

+

+ if (!async_rd_bits.count(addr))

+ continue;

+

+ for (int j = 0; j < mem.width; j++)

+ {

+ int bit_idx = sub * mem.width + j;

+

+ if (port.en[bit_idx] == State::S0)

+ continue;

+

+ dict<RTLIL::SigBit, bool> state;

+

+ find_data_feedback(async_rd_bits.at(addr).at(j), sigmap(port.data[bit_idx]), state, i, bit_idx, paths);

+ }

+ }

+ }

+

+ if (paths.empty())

+ return;

+

+ // Now determine which read ports are actually used only for

+ // feedback paths, and can be removed.

+

+ dict<SigBit, int> feedback_users_count;

+ for (auto &path : paths)

+ feedback_users_count[path.feedback_bit]++;

+

+ pool<SigBit> feedback_ok;

+ for (auto &port : mem.rd_ports)

+ {

+ if (port.clk_enable)

+ continue;

+

+ bool ok = true;

+ for (auto bit : sigmap(port.data))

+ if (sig_users_count[bit] != feedback_users_count[bit])

+ ok = false;

+

+ if (ok)

+ {

+ // This port is going bye-bye.

+ for (auto bit : sigmap(port.data))

+ feedback_ok.insert(bit);

+

+ port.removed = true;

+ }

+ }

+

+ if (feedback_ok.empty())

+ return;

+

+ // Prepare a feedback condition list grouped by port bits.

+

+ dict<std::pair<int, int>, pool<dict<SigBit, bool>>> portbit_conds;

+ for (auto &path : paths)

+ if (feedback_ok.count(path.feedback_bit))

+ portbit_conds[std::make_pair(path.wrport_idx, path.data_bit_idx)].insert(path.condition);

+

+ if (portbit_conds.empty())

+ return;

+

+ // Okay, let's do it.

+

+ log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));

+

+ // If a write port has a feedback path that we're about to bypass,

+ // but also has priority over some other write port, the feedback

+ // path is not necessarily a NOP — it may overwrite the other port.

+ // Emulate this effect by converting the priority to soft logic

+ // (this will affect the other port's enable signal).

+ for (auto &it : portbit_conds)

+ {

+ int wrport_idx = it.first.first;

+ auto &port = mem.wr_ports[wrport_idx];

+

+ for (int i = 0; i < wrport_idx; i++)

+ if (port.priority_mask[i])

+ mem.emulate_priority(i, wrport_idx, &initvals);

+ }

+

+ for (auto &it : portbit_conds)

+ {

+ int wrport_idx = it.first.first;

+ int bit = it.first.second;

+ auto &port = mem.wr_ports[wrport_idx];

+

+ port.en[bit] = conditions_to_logic(it.second, port.en[bit]);

+ log(" Port %d bit %d: added enable logic for %d different cases.\n", wrport_idx, bit, GetSize(it.second));

+ }

+

+ mem.emit();

+

+ for (auto bit : feedback_ok)

+ module->connect(bit, State::Sx);

+

+ design->scratchpad_set_bool("opt.did_something", true);

+ }

+

+ // -------------

+ // Setup and run

+ // -------------

+

+ OptMemFeedbackWorker(RTLIL::Design *design) : design(design) {}

+

+ void operator()(RTLIL::Module* module)

+ {

+ std::vector<Mem> memories = Mem::get_selected_memories(module);

+

+ this->module = module;

+ sigmap.set(module);

+ initvals.set(&sigmap, module);

+ sig_to_mux.clear();

+ conditions_logic_cache.clear();

+

+ sigmap_xmux = sigmap;

+

+ for (auto wire : module->wires()) {

+ if (wire->port_output)

+ for (auto bit : sigmap(wire))

+ sig_users_count[bit]++;

+ }

+

+ for (auto cell : module->cells())

+ {

+ if (cell->type == ID($mux))

+ {

+ RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));

+ RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));

+

+ if (sig_a.is_fully_undef())

+ sigmap_xmux.add(cell->getPort(ID::Y), sig_b);

+ else if (sig_b.is_fully_undef())

+ sigmap_xmux.add(cell->getPort(ID::Y), sig_a);

+ }

+

+ if (cell->type.in(ID($mux), ID($pmux)))

+ {

+ std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));

+ for (int i = 0; i < int(sig_y.size()); i++)

+ sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);

+ }

+

+ for (auto &conn : cell->connections())

+ if (!cell->known() || cell->input(conn.first))

+ for (auto bit : sigmap(conn.second))

+ sig_users_count[bit]++;

+ }

+

+ for (auto &mem : memories)

+ translate_rd_feedback_to_en(mem);

+ }

+};

+

+struct OptMemFeedbackPass : public Pass {

+ OptMemFeedbackPass() : Pass("opt_mem_feedback", "convert memory read-to-write port feedback paths to write enables") { }

+ void help() override

+ {

+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

+ log("\n");

+ log(" opt_mem_feedback [selection]\n");

+ log("\n");

+ log("This pass detects cases where an asynchronous read port is only connected via\n");

+ log("a mux tree to a write port with the same address. When such a connection is\n");

+ log("found, it is replaced with a new condition on an enable signal, allowing\n");

+ log("for removal of the read port.\n");

+ log("\n");

+ }

+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {

+ log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");

+ extra_args(args, 1, design);

+ OptMemFeedbackWorker worker(design);

+

+ for (auto module : design->selected_modules())

+ worker(module);

+ }

+} OptMemFeedbackPass;

+

+PRIVATE_NAMESPACE_END

+

+/*

+ * yosys -- Yosys Open SYnthesis Suite

+ *

+ * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>

+ *

+ * Permission to use, copy, modify, and/or distribute this software for any

+ * purpose with or without fee is hereby granted, provided that the above

+ * copyright notice and this permission notice appear in all copies.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

+ *

+ */

+

+#include "kernel/yosys.h"

+#include "kernel/modtools.h"

+#include "kernel/qcsat.h"

+#include "kernel/mem.h"

+

+USING_YOSYS_NAMESPACE

+PRIVATE_NAMESPACE_BEGIN

+

+struct OptMemPriorityPass : public Pass {

+ OptMemPriorityPass() : Pass("opt_mem_priority", "remove priority relations between write ports that can never collide") { }

+ void help() override

+ {

+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

+ log("\n");

+ log(" opt_mem_priority [selection]\n");

+ log("\n");

+ log("This pass detects cases where one memory write port has priority over another\n");

+ log("even though they can never collide with each other -- ie. there can never be\n");

+ log("a situation where a given memory bit is written by both ports at the same\n");

+ log("time, for example because of always-different addresses, or mutually exclusive\n");

+ log("enable signals. In such cases, the priority relation is removed.\n");

+ log("\n");

+ }

+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {

+ log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");

+ extra_args(args, 1, design);

+

+ ModWalker modwalker(design);

+

+ int total_count = 0;

+ for (auto module : design->selected_modules()) {

+ modwalker.setup(module);

+ for (auto &mem : Mem::get_selected_memories(module)) {

+ bool mem_changed = false;

+ QuickConeSat qcsat(modwalker);

+ for (int i = 0; i < GetSize(mem.wr_ports); i++) {

+ auto &wport1 = mem.wr_ports[i];

+ for (int j = 0; j < GetSize(mem.wr_ports); j++) {

+ auto &wport2 = mem.wr_ports[j];

+ if (!wport1.priority_mask[j])

+ continue;

+ // No mixed width support — we could do it, but

+ // that would complicate code and wouldn't help

+ // anything since we run this pass before

+ // wide ports are created in normal flow.

+ if (wport1.wide_log2 != wport2.wide_log2)

+ continue;

+ // Two ports with priority, let's go.

+ pool<std::pair<SigBit, SigBit>> checked;

+ SigSpec addr1 = wport1.addr;

+ SigSpec addr2 = wport2.addr;

+ int abits = std::max(GetSize(addr1), GetSize(addr2));

+ addr1.extend_u0(abits);

+ addr2.extend_u0(abits);

+ int addr_eq = qcsat.ez->vec_eq(qcsat.importSig(addr1), qcsat.importSig(addr2));

+ bool ok = true;

+ for (int k = 0; k < GetSize(wport1.data); k++) {

+ SigBit wen1 = wport1.en[k];

+ SigBit wen2 = wport2.en[k];

+ if (checked.count({wen1, wen2}))

+ continue;

+ int wen1_sat = qcsat.importSigBit(wen1);

+ int wen2_sat = qcsat.importSigBit(wen2);

+ qcsat.prepare();

+ if (qcsat.ez->solve(wen1_sat, wen2_sat, addr_eq)) {

+ ok = false;

+ break;

+ }

+ checked.insert({wen1, wen2});

+ }

+ if (ok) {

+ total_count++;

+ mem_changed = true;

+ wport1.priority_mask[j] = false;

+ }

+ }

+ }

+ if (mem_changed)

+ mem.emit();

+ }

+ }

+

+ if (total_count)

+ design->scratchpad_set_bool("opt.did_something", true);

+ log("Performed a total of %d transformations.\n", total_count);

+ }

+} OptMemPriorityPass;

+

+PRIVATE_NAMESPACE_END

+

+/*

+ * yosys -- Yosys Open SYnthesis Suite

+ *

+ * Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>

+ *

+ * Permission to use, copy, modify, and/or distribute this software for any

+ * purpose with or without fee is hereby granted, provided that the above

+ * copyright notice and this permission notice appear in all copies.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

+ *

+ */

+

+#include "kernel/yosys.h"

+#include "kernel/mem.h"

+

+USING_YOSYS_NAMESPACE

+PRIVATE_NAMESPACE_BEGIN

+

+struct OptMemWidenPass : public Pass {

+ OptMemWidenPass() : Pass("opt_mem_widen", "optimize memories where all ports are wide") { }

+ void help() override

+ {

+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

+ log("\n");

+ log(" opt_mem_widen [options] [selection]\n");

+ log("\n");

+ log("This pass looks for memories where all ports are wide and adjusts the base\n");

+ log("memory width up until that stops being the case.\n");

+ log("\n");

+ }

+ void execute(std::vector<std::string> args, RTLIL::Design *design) override

+ {

+ log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n");

+

+ size_t argidx;

+ for (argidx = 1; argidx < args.size(); argidx++) {

+ // if (args[argidx] == "-nomux") {

+ // mode_nomux = true;

+ // continue;

+ // }

+ break;

+ }

+ extra_args(args, argidx, design);

+

+ int total_count = 0;

+ for (auto module : design->selected_modules()) {

+ for (auto &mem : Mem::get_selected_memories(module)) {

+ // If the memory has no read ports, opt_clean will remove it

+ // instead.

+ if (mem.rd_ports.empty())

+ continue;

+ int factor_log2 = mem.rd_ports[0].wide_log2;

+ for (auto &port : mem.rd_ports)

+ if (port.wide_log2 < factor_log2)

+ factor_log2 = port.wide_log2;

+ for (auto &port : mem.wr_ports)

+ if (port.wide_log2 < factor_log2)

+ factor_log2 = port.wide_log2;

+ if (factor_log2 == 0)

+ continue;

+ log("Widening base width of memory %s in module %s by factor %d.\n", log_id(mem.memid), log_id(module->name), 1 << factor_log2);

+ total_count++;

+ // The inits are too messy to expand one-by-one, for they may

+ // collide with one another after expansion. Just hit it with

+ // a hammer.

+ bool has_init = !mem.inits.empty();

+ Const init_data;

+ if (has_init) {

+ init_data = mem.get_init_data();

+ mem.clear_inits();

+ }

+ mem.width <<= factor_log2;

+ mem.size >>= factor_log2;

+ mem.start_offset >>= factor_log2;

+ if (has_init) {

+ MemInit new_init;

+ new_init.addr = mem.start_offset;

+ new_init.data = init_data;

+ new_init.en = Const(State::S1, mem.width);

+ mem.inits.push_back(new_init);

+ }

+ for (auto &port : mem.rd_ports) {

+ port.wide_log2 -= factor_log2;

+ port.addr = port.addr.extract_end(factor_log2);

+ }

+ for (auto &port : mem.wr_ports) {

+ port.wide_log2 -= factor_log2;

+ port.addr = port.addr.extract_end(factor_log2);

+ }

+ mem.emit();

+ }

+ }

+

+ if (total_count)

+ design->scratchpad_set_bool("opt.did_something", true);

+ log("Performed a total of %d transformations.\n", total_count);

+ }

+} OptMemWidenPass;

+

+PRIVATE_NAMESPACE_END

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/ffinit.h"

+ FfInitVals initvals;

+ sig = initvals(it.second);

+ if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell1->type)) {

+ conn1[it.first] = initvals(it.second);

+ conn2[it.first] = initvals(cell2->getPort(it.first));

+ initvals.set(&assign_map, module);

+ Const init = initvals(other_sig);

+ initvals.remove_init(it.second);

+ initvals.remove_init(other_sig);

+ initvals.set_init(other_sig, init);

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ if (bits[i] >= 0) {

+ if (knowledge.known_inactive.at(bits[i])) {

+ sig[i] = State::S0;

+ did_something = true;

+ } else

+ if (knowledge.known_active.at(bits[i])) {

+ sig[i] = State::S1;

+ if (width) {

+ sig[i] = ctrl_bits.at(bits[i]) == port_idx ? State::S1 : State::S0;

+ } else {

+ sig[i] = State::S0;

+ }

+ if (width) {

+ if (++port_off == width)

+ port_idx++, port_off=0;

+ }

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ void opt_pmux(RTLIL::Cell *cell)

+ module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));

+ did_something = true;

+ total_count++;

+ return;

+

+ if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {

+ log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));

+ did_something = true;

+ total_count++;

+ void opt_bmux(RTLIL::Cell *cell)

+ RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));

+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));

+ int width = cell->getParam(ID::WIDTH).as_int();

+

+ RTLIL::SigSpec new_sig_a, new_sig_s;

+ dict<RTLIL::SigBit, int> handled_bits;

+

+ // 0 and up: index of new_sig_s bit

+ // -1: const 0

+ // -2: const 1

+ std::vector<int> swizzle;

+

+ for (int i = 0; i < sig_s.size(); i++)

+ {

+ SigBit bit = sig_s[i];

+ if (bit == State::S0) {

+ swizzle.push_back(-1);

+ } else if (bit == State::S1) {

+ swizzle.push_back(-2);

+ } else {

+ auto it = handled_bits.find(bit);

+ if (it == handled_bits.end()) {

+ int new_idx = GetSize(new_sig_s);

+ new_sig_s.append(bit);

+ handled_bits[bit] = new_idx;

+ swizzle.push_back(new_idx);

+ } else {

+ swizzle.push_back(it->second);

+ }

+ }

+ }

+

+ for (int i = 0; i < (1 << GetSize(new_sig_s)); i++) {

+ int idx = 0;

+ for (int j = 0; j < GetSize(sig_s); j++) {

+ if (swizzle[j] == -1) {

+ // const 0.

+ } else if (swizzle[j] == -2) {

+ // const 1.

+ idx |= 1 << j;

+ } else {

+ if (i & 1 << swizzle[j])

+ idx |= 1 << j;

+ }

+ }

+ new_sig_a.append(sig_a.extract(idx * width, width));

+ }

+

+ if (new_sig_s.size() == 0)

+ {

+ module->connect(cell->getPort(ID::Y), new_sig_a);

+ assign_map.add(cell->getPort(ID::Y), new_sig_a);

+ module->remove(cell);

+ did_something = true;

+ total_count++;

+ return;

+ }

+

+ if (new_sig_s.size() == 1)

+ {

+ cell->type = ID($mux);

+ cell->setPort(ID::A, new_sig_a.extract(0, width));

+ cell->setPort(ID::B, new_sig_a.extract(width, width));

+ cell->setPort(ID::S, new_sig_s);

+ cell->parameters.erase(ID::S_WIDTH);

+ did_something = true;

+ total_count++;

+ return;

+ }

+

+ if (new_sig_s.size() != sig_s.size()) {

+ log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));

+ did_something = true;

+ total_count++;

+ cell->setPort(ID::A, new_sig_a);

+ cell->setPort(ID::S, new_sig_s);

+ cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());

+ }

+ }

+

+ void opt_demux(RTLIL::Cell *cell)

+ {

+ RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));

+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));

+ int width = cell->getParam(ID::WIDTH).as_int();

+

+ RTLIL::SigSpec new_sig_y, new_sig_s;

+ dict<RTLIL::SigBit, int> handled_bits;

+

+ // 0 and up: index of new_sig_s bit

+ // -1: const 0

+ // -2: const 1

+ std::vector<int> swizzle;

+

+ for (int i = 0; i < sig_s.size(); i++)

+ {

+ SigBit bit = sig_s[i];

+ if (bit == State::S0) {

+ swizzle.push_back(-1);

+ } else if (bit == State::S1) {

+ swizzle.push_back(-2);

+ } else {

+ auto it = handled_bits.find(bit);

+ if (it == handled_bits.end()) {

+ int new_idx = GetSize(new_sig_s);

+ new_sig_s.append(bit);

+ handled_bits[bit] = new_idx;

+ swizzle.push_back(new_idx);

+ } else {

+ swizzle.push_back(it->second);

+ }

+ }

+ }

+

+ pool<int> nonzero_idx;

+

+ for (int i = 0; i < (1 << GetSize(new_sig_s)); i++) {

+ int idx = 0;

+ for (int j = 0; j < GetSize(sig_s); j++) {

+ if (swizzle[j] == -1) {

+ // const 0.

+ } else if (swizzle[j] == -2) {

+ // const 1.

+ idx |= 1 << j;

+ } else {

+ if (i & 1 << swizzle[j])

+ idx |= 1 << j;

+ }

+ }

+ log_assert(!nonzero_idx.count(idx));

+ nonzero_idx.insert(idx);

+ new_sig_y.append(sig_y.extract(idx * width, width));

+ }

+

+ if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0)

+ return;

+

+ log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));

+ did_something = true;

+ total_count++;

+

+ for (int i = 0; i < (1 << GetSize(sig_s)); i++) {

+ if (!nonzero_idx.count(i)) {

+ SigSpec slice = sig_y.extract(i * width, width);

+ module->connect(slice, Const(State::S0, width));

+ assign_map.add(slice, Const(State::S0, width));

+ }

+ }

+

+ if (new_sig_s.size() == 0)

+ {

+ module->connect(new_sig_y, cell->getPort(ID::A));

+ assign_map.add(new_sig_y, cell->getPort(ID::A));

+ module->remove(cell);

+ }

+ else

+ {

+ cell->setPort(ID::S, new_sig_s);

+ cell->setPort(ID::Y, new_sig_y);

+ cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());

+ }

+ }

+

+ bool opt_mux_bits(RTLIL::Cell *cell)

+ {

+ SigSpec sig_a = assign_map(cell->getPort(ID::A));

+ SigSpec sig_b;

+ SigSpec sig_y = assign_map(cell->getPort(ID::Y));

+ int width = GetSize(sig_y);

+

+ if (cell->type != ID($bmux))

+ sig_b = assign_map(cell->getPort(ID::B));

+ dict<SigSpec, SigBit> consolidated_in_tuples;

+ std::vector<int> swizzle;

+ for (int i = 0; i < width; i++)

+ SigSpec in_tuple;

+ in_tuple.append(sig_a[i]);

+ for (int j = i; j < GetSize(sig_a); j += width) {

+ in_tuple.append(sig_a[j]);

+ if (sig_a[j] != in_tuple[0])

+ all_tuple_bits_same = false;

+ }

+ for (int j = i; j < GetSize(sig_b); j += width) {

+ in_tuple.append(sig_b[j]);

+ if (sig_b[j] != in_tuple[0])

+ old_sig_conn.first.append(sig_y[i]);

+ old_sig_conn.second.append(sig_a[i]);

+ continue;

+

+ auto it = consolidated_in_tuples.find(in_tuple);

+ if (it == consolidated_in_tuples.end())

+ consolidated_in_tuples[in_tuple] = sig_y[i];

+ swizzle.push_back(i);

+ old_sig_conn.first.append(sig_y[i]);

+ old_sig_conn.second.append(it->second);

+ if (GetSize(swizzle) != width)

+ if (cell->type != ID($bmux)) {

+ log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));

+ } else {

+ log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::Y)));

+ if (swizzle.empty()) {

+ module->remove(cell);

+ } else {

+ SigSpec new_sig_a;

+ for (int i = 0; i < GetSize(sig_a); i += width)

+ for (int j: swizzle)

+ new_sig_a.append(sig_a[i+j]);

+ cell->setPort(ID::A, new_sig_a);

+

+ if (cell->type != ID($bmux)) {

+ SigSpec new_sig_b;

+ for (int i = 0; i < GetSize(sig_b); i += width)

+ for (int j: swizzle)

+ new_sig_b.append(sig_b[i+j]);

+ cell->setPort(ID::B, new_sig_b);

+ SigSpec new_sig_y;

+ for (int j: swizzle)

+ new_sig_y.append(sig_y[j]);

+ cell->setPort(ID::Y, new_sig_y);

+

+ cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));

+

+ if (cell->type != ID($bmux)) {

+ log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));

+ } else {

+ log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::Y)));

+ }

+ }

+ module->connect(old_sig_conn);

+

+ did_something = true;

+ total_count++;

+ }

+ return swizzle.empty();

+ }

+

+ bool opt_demux_bits(RTLIL::Cell *cell) {

+ SigSpec sig_a = assign_map(cell->getPort(ID::A));

+ SigSpec sig_y = assign_map(cell->getPort(ID::Y));

+ int width = GetSize(sig_a);

+

+ RTLIL::SigSig old_sig_conn;

+

+ dict<SigBit, int> handled_bits;

+ std::vector<int> swizzle;

+

+ for (int i = 0; i < width; i++)

+ {

+ if (sig_a[i] == State::S0)

+ {

+ for (int j = i; j < GetSize(sig_y); j += width)

+ {

+ old_sig_conn.first.append(sig_y[j]);

+ old_sig_conn.second.append(State::S0);

+ }

+ continue;

+ }

+ auto it = handled_bits.find(sig_a[i]);

+ if (it == handled_bits.end())

+ {

+ handled_bits[sig_a[i]] = i;

+ swizzle.push_back(i);

+ }

+ else

+ {

+ for (int j = 0; j < GetSize(sig_y); j += width)

+ {

+ old_sig_conn.first.append(sig_y[i+j]);

+ old_sig_conn.second.append(sig_y[it->second+j]);

+ }

+ }

+ }

+

+ if (GetSize(swizzle) != width)

+ {

+ log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());

+ log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::Y)));

+

+ if (swizzle.empty()) {

+ module->remove(cell);

+ } else {

+ SigSpec new_sig_a;

+ for (int j: swizzle)

+ new_sig_a.append(sig_a[j]);

+ cell->setPort(ID::A, new_sig_a);

+

+ SigSpec new_sig_y;

+ for (int i = 0; i < GetSize(sig_y); i += width)

+ for (int j: swizzle)

+ new_sig_y.append(sig_y[i+j]);

+ cell->setPort(ID::Y, new_sig_y);

+

+ cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));

+

+ log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),

+ log_signal(cell->getPort(ID::Y)));

+ }

+

+ log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));

+ return swizzle.empty();

+ if (cell->type.in(ID($mem), ID($mem_v2)))

+ if (cell->type.in(ID($memwr), ID($memwr_v2)))

+ for (auto cell : module->selected_cells())

+ if (!cell->type.in(ID($mux), ID($pmux), ID($bmux), ID($demux)))

+ continue;

+

+ if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {

+ if (cell->type == ID($demux)) {

+ if (opt_demux_bits(cell))

+ continue;

+ } else {

+ if (opt_mux_bits(cell))

+ continue;

+ }

+ }

+

+ if (cell->type.in(ID($mux), ID($pmux)))

+ opt_pmux(cell);

+

+ if (cell->type == ID($bmux))

+ opt_bmux(cell);

+ if (cell->type == ID($demux))

+ opt_demux(cell);

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap)

+ auto sig = sigmap(cell->getPort(port_name));

+void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap)

+ if (decode_port(op, ID::A, sigmap) == operand)

+ auto operand = decode_port(op, muxed_port_name, sigmap);

+ max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());

+ for (auto &operand : muxed_operands) {

+ if (operand.sign != muxed_operands[0].sign)

+ operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));

+ }

+ int conn_width = ports[0].sig.size();

+ int conn_mux_offset = ports[0].mux_port_offset;

+ int conn_op_offset = ports[0].op_outsig_offset;

+

+ // Make a new wire to avoid false equivalence with whatever the former shared output was connected to.

+ Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);

+ SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);

+ for (int i = 0; i < GetSize(ports); i++) {

+ auto &p = ports[i];

+ auto &op = muxed_operands[i];

+ if (p.mux_port_id == GetSize(mux_s)) {

+ shared_pmux_a = op.sig;

+ mux_a.replace(conn_mux_offset, new_sig_out);

+ } else {

+ shared_pmux_b.append(op.sig);

+ mux_b.replace(p.mux_port_id * mux_a.size() + conn_mux_offset, new_sig_out);

+ SigSpec mux_to_oper;

+ if (GetSize(shared_pmux_s) == 1) {

+ mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);

+ } else {

+ mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);

+ }

+ shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));

+ shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));

+ shared_op->setPort(ID::Y, new_out);

+ shared_op->setParam(ID::Y_WIDTH, GetSize(new_out));

+ if (decode_port(shared_op, ID::A, sigmap) == operand) {

+void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand, const SigMap &sigmap)

+ if (decode_port(op, ID::A, sigmap) == shared_operand) {

+ auto operand = decode_port(op, muxed_port_name, sigmap);

+ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users, const SigMap &sigmap)

+ oper = decode_port(op_a, port_name, sigmap);

+ SigMap sigmap(module);

+

+ dict<RTLIL::SigBit, int> bit_users;

+

+ for (auto cell : module->cells())

+ for (auto conn : cell->connections())

+ for (auto bit : conn.second)

+ bit_users[sigmap(bit)]++;

+

+ for (auto wire : module->wires())

+ if (wire->port_id != 0)

+ for (auto bit : SigSpec(wire))

+ bit_users[sigmap(bit)]++;

+ dict<RTLIL::SigBit, std::pair<RTLIL::Cell *, int>> op_outbit_to_outsig;

+ for (auto cell : module->selected_cells()) {

+ bool skip = false;

+ for (auto outbit : sigmap(cell->getPort(port_name)))

+ if (bit_users[outbit] > 1)

+ skip = true;

+ if (skip)

+ continue;

+

+ auto mux_insig = sigmap(cell->getPort(ID::Y));

+ for (int i = 0; i < GetSize(mux_insig); i++)

+ op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i);

+ auto op_insig = decode_port(cell, port_name, sigmap);

+ std::vector<merged_op_t> merged_ops;

+ for (auto mux : module->selected_cells()) {

+ if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))

+ continue;

+ int mux_port_size = GetSize(mux->getPort(ID::A));

+ int mux_port_num = GetSize(mux->getPort(ID::S)) + 1;

+ RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)});

+ std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);

+ int found = 0;

+ for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {

+ SigSpec mux_insig;

+ if (mux_port_id == mux_port_num - 1) {

+ mux_insig = sigmap(mux->getPort(ID::A));

+ } else {

+ mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size));

+ }

+ for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {

+ if (!op_outbit_to_outsig.count(mux_insig[mux_port_offset]))

+ continue;

+ RTLIL::Cell *cell;

+ int op_outsig_offset;

+ std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]);

+ SigSpec op_outsig = sigmap(cell->getPort(ID::Y));

+ int op_outsig_size = GetSize(op_outsig);

+ int op_conn_width = 0;

+

+ while (mux_port_offset + op_conn_width < mux_port_size &&

+ op_outsig_offset + op_conn_width < op_outsig_size &&

+ mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])

+ op_conn_width++;

+

+ log_assert(op_conn_width >= 1);

+

+ bool skip = false;

+ for (int i = 0; i < op_outsig_size; i++) {

+ int expected = 1;

+ if (i >= op_outsig_offset && i < op_outsig_offset + op_conn_width)

+ expected = 2;

+ if (bit_users[op_outsig[i]] != expected)

+ skip = true;

+ }

+ if (skip) {

+ mux_port_offset += op_conn_width;

+ mux_port_offset--;

+ continue;

+ }

+

+ OpMuxConn inp = {

+ op_outsig.extract(op_outsig_offset, op_conn_width),

+ mux,

+ cell,

+ mux_port_id,

+ mux_port_offset,

+ op_outsig_offset,

+ };

+

+ mux_port_conns[mux_port_id].insert(inp);

+

+ mux_port_offset += op_conn_width;

+ mux_port_offset--;

+ found++;

+ }

+ }

+

+ if (found < 2)

+ continue;

+ auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users, sigmap);

+ check_muxed_operands(mergeable_conns, shared_operand, sigmap);

+ merged_ops.push_back(merged_op_t{mux, merged_ports, shared_operand});

+ merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/ffinit.h"

+ FfInitVals initvals;

+ initvals.set(&sigmap, module);

+ if (initvals(bit) == State::S1) {

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/qcsat.h"

+ if (cell->type.in(ID($memrd), ID($memrd_v2))) {

+ if (c1->type.in(ID($memrd), ID($memrd_v2)))

+ if (c1->parameters.at(ID::WIDTH) != c2->parameters.at(ID::WIDTH))

+ return false;

+

+ if (c1->type.in(ID($memrd), ID($memrd_v2)))

+ QuickConeSat qcsat(modwalker);

+ if (config.opt_fast) {

+ qcsat.max_cell_outs = 3;

+ qcsat.max_cell_count = 100;

+ }

+ cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));

+ other_cell_active.push_back(qcsat.ez->vec_eq(qcsat.importSig(p.first), qcsat.importSig(p.second)));

+ qcsat.prepare();

+ int sub1 = qcsat.ez->expression(qcsat.ez->OpOr, cell_active);

+ if (!qcsat.ez->solve(sub1)) {

+ int sub2 = qcsat.ez->expression(qcsat.ez->OpOr, other_cell_active);

+ if (!qcsat.ez->solve(sub2)) {

+ qcsat.ez->non_incremental();

+ std::vector<int> sat_model = qcsat.importSig(all_ctrl_signals);

+ qcsat.ez->assume(qcsat.ez->AND(sub1, sub2));

+ GetSize(sat_cells), qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());

+ if (qcsat.ez->solve(sat_model, sat_model_values)) {

+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>

+#include "kernel/ffinit.h"

+ FfInitVals initvals;

+ Const initval = initvals(sig_q), rst_value;

+ initvals.remove_init(sig_q[i]);

+ initvals.remove_init(sig_q[i]);

+ initvals.remove_init(sig_q[i]);

+ initvals.set(&init_attr_sigmap, module);

+ if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) {