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-rw-r--r--passes/opt/opt.cc4
-rw-r--r--passes/opt/opt_clean.cc20
-rw-r--r--passes/opt/opt_const.cc14
-rw-r--r--passes/opt/opt_muxtree.cc4
-rw-r--r--passes/opt/opt_reduce.cc4
-rw-r--r--passes/opt/opt_rmdff.cc10
-rw-r--r--passes/opt/opt_share.cc4
-rw-r--r--passes/opt/share.cc2
8 files changed, 45 insertions, 17 deletions
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index b20521d1e..ea454b333 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -22,6 +22,9 @@
#include <stdlib.h>
#include <stdio.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptPass : public Pass {
OptPass() : Pass("opt", "perform simple optimizations") { }
virtual void help()
@@ -142,3 +145,4 @@ struct OptPass : public Pass {
}
} OptPass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 5046752f9..d589518aa 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -25,12 +25,15 @@
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
-static CellTypes ct, ct_reg, ct_all;
-static int count_rm_cells, count_rm_wires;
+CellTypes ct, ct_reg, ct_all;
+int count_rm_cells, count_rm_wires;
-static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
+void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
@@ -93,7 +96,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
}
}
-static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
+int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
count -= w->attributes.count("\\src");
@@ -101,7 +104,7 @@ static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
return count;
}
-static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
+bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
{
RTLIL::Wire *w1 = s1.wire;
RTLIL::Wire *w2 = s2.wire;
@@ -136,7 +139,7 @@ static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs,
return w2->name < w1->name;
}
-static bool check_public_name(RTLIL::IdString id)
+bool check_public_name(RTLIL::IdString id)
{
const std::string &id_str = id.str();
if (id_str[0] == '$')
@@ -148,7 +151,7 @@ static bool check_public_name(RTLIL::IdString id)
return true;
}
-static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
+void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
{
SigPool register_signals;
SigPool connected_signals;
@@ -285,7 +288,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
log(" removed %d unused temporary wires.\n", del_wires_count);
}
-static void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
+void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
@@ -419,3 +422,4 @@ struct CleanPass : public Pass {
}
} CleanPass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index f9b78c053..7c9fca961 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -26,9 +26,12 @@
#include <stdio.h>
#include <algorithm>
-static bool did_something;
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
-static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
+bool did_something;
+
+void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
{
CellTypes ct(design);
SigMap sigmap(module);
@@ -70,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
}
}
-static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
+void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);
@@ -85,7 +88,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
did_something = true;
}
-static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
+bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
{
std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
@@ -183,7 +186,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
return true;
}
-static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
{
if (!design->selected(module))
return;
@@ -1006,3 +1009,4 @@ struct OptConstPass : public Pass {
}
} OptConstPass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 2c5dcf668..88ae43f0e 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -25,6 +25,9 @@
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
struct OptMuxtreeWorker
@@ -438,3 +441,4 @@ struct OptMuxtreePass : public Pass {
}
} OptMuxtreePass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index e9e2bb399..302deb9bd 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -25,6 +25,9 @@
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptReduceWorker
{
RTLIL::Design *design;
@@ -378,3 +381,4 @@ struct OptReducePass : public Pass {
}
} OptReducePass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 48f406f65..c7e92ddc1 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -23,10 +23,13 @@
#include <stdlib.h>
#include <stdio.h>
-static SigMap assign_map, dff_init_map;
-static SigSet<RTLIL::Cell*> mux_drivers;
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
-static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
+SigMap assign_map, dff_init_map;
+SigSet<RTLIL::Cell*> mux_drivers;
+
+bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
{
RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
RTLIL::Const val_cp, val_rp, val_rv;
@@ -215,3 +218,4 @@ struct OptRmdffPass : public Pass {
}
} OptRmdffPass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 4b76a5a2d..33115349c 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -28,6 +28,9 @@
#define USE_CELL_HASH_CACHE
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptShareWorker
{
RTLIL::Design *design;
@@ -319,3 +322,4 @@ struct OptSharePass : public Pass {
}
} OptSharePass;
+PRIVATE_NAMESPACE_END
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 74b049bb6..03f6527c0 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -23,6 +23,7 @@
#include "kernel/modtools.h"
#include "kernel/utils.h"
+USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ShareWorkerConfig
@@ -1168,4 +1169,3 @@ struct SharePass : public Pass {
} SharePass;
PRIVATE_NAMESPACE_END
-