1 files changed, 170 insertions, 61 deletions

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 7003092bb..fbf498109 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,87 +1,137 @@
 pattern ice40_dsp
 
 state <SigBit> clock
-state <bool> clock_pol clock_vld
-state <SigSpec> sigA sigB sigY sigS
+state <bool> clock_pol cd_signed
+state <SigSpec> sigA sigB sigCD sigH sigO
 state <Cell*> addAB muxAB
 
 match mul
-	select mul->type.in($mul)
+	select mul->type.in($mul, \SB_MAC16)
 	select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
-	select GetSize(mul->getPort(\Y)) > 10
 endmatch
 
+code sigA sigB sigH
+	SigSpec O;
+	if (mul->type == $mul)
+		O = mul->getPort(\Y);
+	else if (mul->type == \SB_MAC16)
+		O = mul->getPort(\O);
+	else log_abort();
+	if (GetSize(O) <= 10)
+		reject;
+
+	sigA = port(mul, \A);
+	int i;
+	for (i = GetSize(sigA)-1; i > 0; i--)
+		if (sigA[i] != sigA[i-1])
+			break;
+	// Do not remove non-const sign bit
+	if (sigA[i].wire)
+		++i;
+	sigA.remove(i, GetSize(sigA)-i);
+	sigB = port(mul, \B);
+	for (i = GetSize(sigB)-1; i > 0; i--)
+		if (sigB[i] != sigB[i-1])
+			break;
+	// Do not remove non-const sign bit
+	if (sigB[i].wire)
+		++i;
+	sigB.remove(i, GetSize(sigB)-i);
+
+	// Only care about those bits that are used
+	for (i = 0; i < GetSize(O); i++) {
+		if (nusers(O[i]) <= 1)
+			break;
+		sigH.append(O[i]);
+	}
+	log_assert(nusers(O.extract_end(i)) <= 1);
+endcode
+
 match ffA
+	if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
 	select ffA->type.in($dff)
-	// select nusers(port(ffA, \Q)) == 2
-	index <SigSpec> port(ffA, \Q) === port(mul, \A)
+	filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
+	slice offset GetSize(port(ffA, \Q))
+	filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
 	optional
 endmatch
 
-code sigA clock clock_pol clock_vld
-	sigA = port(mul, \A);
-
+code sigA clock clock_pol
 	if (ffA) {
-		sigA = port(ffA, \D);
+		for (auto b : port(ffA, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
 
 		clock = port(ffA, \CLK).as_bit();
 		clock_pol = param(ffA, \CLK_POLARITY).as_bool();
-		clock_vld = true;
+
+		sigA.replace(port(ffA, \Q), port(ffA, \D));
 	}
 endcode
 
 match ffB
+	if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
 	select ffB->type.in($dff)
-	// select nusers(port(ffB, \Q)) == 2
-	index <SigSpec> port(ffB, \Q) === port(mul, \B)
+	filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
+	slice offset GetSize(port(ffB, \Q))
+	filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
 	optional
 endmatch
 
-code sigB clock clock_pol clock_vld
-	sigB = port(mul, \B);
-
+code sigB clock clock_pol
 	if (ffB) {
-		sigB = port(ffB, \D);
+		for (auto b : port(ffB, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
 		SigBit c = port(ffB, \CLK).as_bit();
 		bool cp = param(ffB, \CLK_POLARITY).as_bool();
 
-		if (clock_vld && (c != clock || cp != clock_pol))
+		if (clock != SigBit() && (c != clock || cp != clock_pol))
 			reject;
 
 		clock = c;
 		clock_pol = cp;
-		clock_vld = true;
+
+		sigB.replace(port(ffB, \Q), port(ffB, \D));
 	}
 endcode
 
-match ffY
-	select ffY->type.in($dff)
-	select nusers(port(ffY, \D)) == 2
-	index <SigSpec> port(ffY, \D) === port(mul, \Y)
+match ffFJKG
+	// Ensure pipeline register is not already used
+	if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
+	select ffFJKG->type.in($dff)
+	select nusers(port(ffFJKG, \D)) == 2
+	index <SigSpec> port(ffFJKG, \D) === sigH
 	optional
 endmatch
 
-code sigY clock clock_pol clock_vld
-	sigY = port(mul, \Y);
+code sigH sigO clock clock_pol
+	if (ffFJKG) {
+		sigH = port(ffFJKG, \Q);
+		for (auto b : sigH)
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
 
-	if (ffY) {
-		sigY = port(ffY, \Q);
-		SigBit c = port(ffY, \CLK).as_bit();
-		bool cp = param(ffY, \CLK_POLARITY).as_bool();
+		SigBit c = port(ffFJKG, \CLK).as_bit();
+		bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 
-		if (clock_vld && (c != clock || cp != clock_pol))
+		if (clock != SigBit() && (c != clock || cp != clock_pol))
 			reject;
 
 		clock = c;
 		clock_pol = cp;
-		clock_vld = true;
 	}
+
+	sigO = sigH;
 endcode
 
 match addA
 	select addA->type.in($add)
 	select nusers(port(addA, \A)) == 2
-	index <SigSpec> port(addA, \A) === sigY
+	filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
+	//index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
+	filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
 	optional
 endmatch
 
@@ -89,75 +139,134 @@ match addB
 	if !addA
 	select addB->type.in($add, $sub)
 	select nusers(port(addB, \B)) == 2
-	index <SigSpec> port(addB, \B) === sigY
+	filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
+	//index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
+	filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
 	optional
 endmatch
 
-code addAB sigS
+code addAB sigCD sigO cd_signed
 	if (addA) {
 		addAB = addA;
-		sigS = port(addA, \B);
+		sigCD = port(addAB, \B);
+		cd_signed = param(addAB, \B_SIGNED).as_bool();
 	}
-	if (addB) {
+	else if (addB) {
 		addAB = addB;
-		sigS = port(addB, \A);
+		sigCD = port(addAB, \A);
+		cd_signed = param(addAB, \A_SIGNED).as_bool();
 	}
 	if (addAB) {
+		if (mul->type == \SB_MAC16) {
+			// Ensure that adder is not used
+			if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
+					param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
+				reject;
+		}
+
 		int natural_mul_width = GetSize(sigA) + GetSize(sigB);
-		int actual_mul_width = GetSize(sigY);
-		int actual_acc_width = GetSize(sigS);
+		int actual_mul_width = GetSize(sigH);
+		int actual_acc_width = GetSize(sigCD);
 
 		if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 			reject;
-		if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+		// If accumulator, check adder width and signedness
+		if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
 			reject;
+
+		sigO = port(addAB, \Y);
 	}
 endcode
 
 match muxA
-	if addAB
 	select muxA->type.in($mux)
-	select nusers(port(muxA, \A)) == 2
-	index <SigSpec> port(muxA, \A) === port(addAB, \Y)
+	index <int> nusers(port(muxA, \A)) === 2
+	index <SigSpec> port(muxA, \A) === sigO
 	optional
 endmatch
 
 match muxB
-	if addAB
 	if !muxA
 	select muxB->type.in($mux)
-	select nusers(port(muxB, \B)) == 2
-	index <SigSpec> port(muxB, \B) === port(addAB, \Y)
+	index <int> nusers(port(muxB, \B)) === 2
+	index <SigSpec> port(muxB, \B) === sigO
 	optional
 endmatch
 
-code muxAB
-	muxAB = addAB;
+code muxAB sigO
 	if (muxA)
 		muxAB = muxA;
-	if (muxB)
+	else if (muxB)
 		muxAB = muxB;
+	if (muxAB)
+		sigO = port(muxAB, \Y);
 endcode
 
-match ffS
-	if muxAB
-	select ffS->type.in($dff)
-	select nusers(port(ffS, \D)) == 2
-	index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
-	index <SigSpec> port(ffS, \Q) === sigS
+match ffO
+	// Ensure that register is not already used
+	if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
+	// Ensure that OLOADTOP/OLOADBOT is unused or zero
+	if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
+	if nusers(sigO) == 2
+	select ffO->type.in($dff)
+	filter GetSize(port(ffO, \D)) >= GetSize(sigO)
+	slice offset GetSize(port(ffO, \D))
+	filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
+	optional
+endmatch
+
+match ffO_lo
+	if !ffO && GetSize(sigO) > 16
+	// Ensure that register is not already used
+	if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
+	// Ensure that OLOADTOP/OLOADBOT is unused or zero
+	if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
+	if nusers(sigO.extract(0, 16)) == 2
+	select ffO_lo->type.in($dff)
+	filter GetSize(port(ffO_lo, \D)) >= 16
+	slice offset GetSize(port(ffO_lo, \D))
+	filter offset+GetSize(sigO) <= GetSize(port(ffO_lo, \D)) && port(ffO_lo, \D).extract(offset, 16) == sigO.extract(0, 16)
+	optional
 endmatch
 
-code clock clock_pol clock_vld
-	if (ffS) {
-		SigBit c = port(ffS, \CLK).as_bit();
-		bool cp = param(ffS, \CLK_POLARITY).as_bool();
+code ffO clock clock_pol sigO sigCD cd_signed
+	if (ffO_lo) {
+		log_assert(!ffO);
+		ffO = ffO_lo;
+	}
+	if (ffO) {
+		for (auto b : port(ffO, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
+		SigBit c = port(ffO, \CLK).as_bit();
+		bool cp = param(ffO, \CLK_POLARITY).as_bool();
 
-		if (clock_vld && (c != clock || cp != clock_pol))
+		if (clock != SigBit() && (c != clock || cp != clock_pol))
 			reject;
 
 		clock = c;
 		clock_pol = cp;
-		clock_vld = true;
+
+		sigO.replace(port(ffO, \D), port(ffO, \Q));
+
+		// Loading value into output register is not
+		//   supported unless using accumulator
+		if (muxAB) {
+			if (sigCD != sigO)
+				reject;
+			if (muxA)
+				sigCD = port(muxAB, \B);
+			else if (muxB)
+				sigCD = port(muxAB, \A);
+			else log_abort();
+
+			cd_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
+		}
 	}
+	sigCD.extend_u0(32, cd_signed);
+endcode
+
+code
 	accept;
 endcode