1 files changed, 29 insertions, 10 deletions

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 5dee36a11..7f1958d5d 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,6 +1,7 @@
 pattern xilinx_dsp
 
 state <SigBit> clock
+state <std::set<SigBit>> sigAset sigBset
 state <SigSpec> sigC sigP sigPused
 state <Cell*> addAB
 
@@ -8,33 +9,51 @@ match dsp
 	select dsp->type.in(\DSP48E1)
 endmatch
 
+code sigAset sigBset
+	SigSpec A = port(dsp, \A);
+	A.remove_const();
+	sigAset = A.to_sigbit_set();
+	SigSpec B = port(dsp, \B);
+	B.remove_const();
+	sigBset = B.to_sigbit_set();
+endcode
+
 match ffA
 	if param(dsp, \AREG).as_int() == 0
-	if !port(dsp, \A).remove_const().empty()
+	if !sigAset.empty()
 	select ffA->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffA, \CLK_POLARITY).as_bool()
-	filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
+	filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
 	optional
 endmatch
 
 code clock
-	if (ffA)
+	if (ffA) {
 		clock = port(ffA, \CLK).as_bit();
+
+		for (auto b : port(ffA, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+	}
 endcode
 
 match ffB
 	if param(dsp, \BREG).as_int() == 0
-	if !port(dsp, \B).remove_const().empty()
+	if !sigBset.empty()
 	select ffB->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffB, \CLK_POLARITY).as_bool()
-	filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
+	filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
 	optional
 endmatch
 
 code clock
 	if (ffB) {
+		for (auto b : port(ffB, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
 		SigBit c = port(ffB, \CLK).as_bit();
 
 		if (clock != SigBit() && c != clock)
@@ -65,21 +84,18 @@ match addB
 	index <int> nusers(port(addB, \B)) === 2
 	//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
 	filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
-	filter port(addB, \B) ==  sigP.extract(0, param(addB, \B_WIDTH).as_int())
+	filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int())
 	optional
 endmatch
 
 code addAB sigC sigP
-	bool C_SIGNED = false;
 	if (addA) {
 		addAB = addA;
 		sigC = port(addAB, \B);
-		C_SIGNED = param(addAB, \B_SIGNED).as_bool();
 	}
 	if (addB) {
 		addAB = addB;
 		sigC = port(addAB, \A);
-		C_SIGNED = param(addAB, \B_SIGNED).as_bool();
 	}
 	if (addAB) {
 		// Ensure that adder is not used
@@ -97,7 +113,6 @@ code addAB sigC sigP
 		//	reject;
 
 		sigP = port(addAB, \Y);
-                sigC.extend_u0(32, C_SIGNED);
 	}
 endcode
 
@@ -150,6 +165,10 @@ code ffP clock
 //		ffP = ffY;
 
 	if (ffP) {
+		for (auto b : port(ffP, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
+
 		SigBit c = port(ffP, \CLK).as_bit();
 
 		if (clock != SigBit() && c != clock)