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-rw-r--r--passes/pmgen/xilinx_dsp.pmg15
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 3523db3a4..8a2c2caf5 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock
}
else
sigM = P;
+ // TODO: Check if necessary
+ // This sigM could have no users if downstream $add
+ // is narrower than $mul result, for example
+ if (sigM.empty())
+ reject;
clock = port(dsp, \CLK, SigBit());
endcode
@@ -154,6 +159,16 @@ match preAdd
optional
endmatch
+code sigA sigD
+ // TODO: Check if this is necessary?
+ if (preAdd) {
+ sigA = port(preAdd, \A);
+ sigD = port(preAdd, \B);
+ if (GetSize(sigA) < GetSize(sigD))
+ std::swap(sigA, sigD);
+ }
+endcode
+
// (4) If pre-adder was present, find match 'A' input for A2REG
// If pre-adder was not present, move ADREG to A2REG
// Then match 'A' input for A1REG