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-rw-r--r--passes/pmgen/xilinx_dsp.pmg12
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 05837d057..7db8e95a6 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -290,8 +290,8 @@ endmatch
code argQ
if (ff) {
- for (auto b : argQ)
- if (b.wire->get_bool_attribute(\keep))
+ for (auto c : argQ.chunks())
+ if (c.wire->get_bool_attribute(\keep))
reject;
if (clock != SigBit()) {
@@ -447,9 +447,13 @@ code
if (dff) {
dffQ = port(dff, \Q);
- for (auto b : dffQ)
- if (b.wire->get_bool_attribute(\keep))
+ for (auto c : dffQ.chunks()) {
+ if (c.wire->get_bool_attribute(\keep))
reject;
+ Const init = c.wire->attributes.at(\init, State::Sx);
+ if (!init.is_fully_undef() && !init.is_fully_zero())
+ reject;
+ }
if (clock != SigBit()) {
if (port(dff, \CLK) != clock)