diff options
Diffstat (limited to 'passes/proc/proc_dlatch.cc')
| -rw-r--r-- | passes/proc/proc_dlatch.cc | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index e7c8a80dd..8340e1431 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -19,6 +19,7 @@ #include "kernel/register.h" #include "kernel/sigtools.h" +#include "kernel/ffinit.h" #include "kernel/consteval.h" #include "kernel/log.h" #include <sstream> @@ -32,6 +33,7 @@ struct proc_dlatch_db_t { Module *module; SigMap sigmap; + FfInitVals initvals; pool<Cell*> generated_dlatches; dict<Cell*, vector<SigBit>> mux_srcbits; @@ -40,6 +42,8 @@ struct proc_dlatch_db_t proc_dlatch_db_t(Module *module) : module(module), sigmap(module) { + initvals.set(&sigmap, module); + for (auto cell : module->cells()) { if (cell->type.in(ID($mux), ID($pmux))) @@ -69,9 +73,11 @@ struct proc_dlatch_db_t } for (auto wire : module->wires()) + { if (wire->port_input) for (auto bit : sigmap(wire)) sigusers[bit]++; + } } bool quickcheck(const SigSpec &haystack, const SigSpec &needle) @@ -336,7 +342,6 @@ struct proc_dlatch_db_t void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) { - std::vector<RTLIL::SyncRule*> new_syncs; RTLIL::SigSig latches_bits, nolatches_bits; dict<SigBit, SigBit> latches_out_in; dict<SigBit, int> latches_hold; @@ -345,7 +350,6 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) for (auto sr : proc->syncs) { if (sr->type != RTLIL::SyncType::STa) { - new_syncs.push_back(sr); continue; } @@ -367,8 +371,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) for (int i = 0; i < GetSize(ss.first); i++) latches_out_in[ss.first[i]] = ss.second[i]; } - - delete sr; + sr->actions.clear(); } latches_out_in.sort(); @@ -393,6 +396,13 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) else log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + for (auto &bit : lhs) { + State val = db.initvals(bit); + if (db.initvals(bit) != State::Sx) { + log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str()); + } + db.initvals.remove_init(bit); + } db.module->connect(lhs, rhs); offset += chunk.width; } @@ -428,8 +438,6 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) offset += width; } - - new_syncs.swap(proc->syncs); } struct ProcDlatchPass : public Pass { |