diff options
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 4 | ||||
| -rw-r--r-- | passes/proc/proc_clean.cc | 3 | ||||
| -rw-r--r-- | passes/proc/proc_prune.cc | 16 |
3 files changed, 10 insertions, 13 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index d069f152a..c606deb88 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -55,7 +55,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (!cell->getPort("\\A").as_bool()) polarity = !polarity; @@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (cell->getPort("\\A").as_bool()) polarity = !polarity; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 97f4c6573..114c6ab03 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -69,8 +69,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did did_something = true; for (auto &action : sw->cases[0]->actions) parent->actions.push_back(action); - for (auto sw2 : sw->cases[0]->switches) - parent->switches.push_back(sw2); + parent->switches.insert(parent->switches.begin(), sw->cases[0]->switches.begin(), sw->cases[0]->switches.end()); sw->cases[0]->switches.clear(); delete sw->cases[0]; sw->cases.clear(); diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index b47ee79c2..d4aee9df0 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -65,8 +65,7 @@ struct PruneWorker pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected); assigned.insert(sw_assigned.begin(), sw_assigned.end()); } - pool<RTLIL::SigSig> remove; - for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) { + for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) { RTLIL::SigSpec lhs = sigmap(it->first); bool redundant = true; for (auto &bit : lhs) { @@ -75,9 +74,10 @@ struct PruneWorker break; } } + bool remove = false; if (redundant) { removed_count++; - remove.insert(*it); + remove = true; } else { if (root) { bool promotable = true; @@ -99,7 +99,7 @@ struct PruneWorker } promoted_count++; module->connect(conn); - remove.insert(*it); + remove = true; } } for (auto &bit : lhs) @@ -109,11 +109,9 @@ struct PruneWorker if (bit.wire) affected.insert(bit); } - } - for (auto it = cs->actions.begin(); it != cs->actions.end(); ) { - if (remove[*it]) { - it = cs->actions.erase(it); - } else it++; + if (remove) + cs->actions.erase((it++).base() - 1); + else it++; } return assigned; } |