8 files changed, 30 insertions, 15 deletions
diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc
index 577ff6bf5..6998cef7e 100644
--- a/passes/proc/proc.cc
+++ b/passes/proc/proc.cc
@@ -57,7 +57,7 @@ struct ProcPass : public Pass {
 	{
 		std::string global_arst;
 
-		log_header("Executing PROC pass (convert processes to netlists).\n");
+		log_header(design, "Executing PROC pass (convert processes to netlists).\n");
 		log_push();
 
 		size_t argidx;
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 1da237283..216b00ddd 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -226,7 +226,7 @@ struct ProcArstPass : public Pass {
 		std::string global_arst;
 		bool global_arst_neg = false;
 
-		log_header("Executing PROC_ARST pass (detect async resets in processes).\n");
+		log_header(design, "Executing PROC_ARST pass (detect async resets in processes).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 35801951a..7dbabc211 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -156,7 +156,7 @@ struct ProcCleanPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		int total_count = 0;
-		log_header("Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
+		log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
 
 		extra_args(args, 1, design);
 
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 637131399..f532990c2 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -369,7 +369,7 @@ struct ProcDffPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_DFF pass (convert process syncs to FFs).\n");
+		log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
 
 		extra_args(args, 1, design);
 
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index e37d81ddd..c339ac682 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -292,7 +292,7 @@ struct ProcDlatchPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_DLATCH pass (convert process syncs to latches).\n");
+		log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
 
 		extra_args(args, 1, design);
 
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 633d4e58a..0c8fb83dc 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 					log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
 
 				int offset = 0;
-				for (auto &lhs_c : lhs.chunks()) {
-					if (lhs_c.wire != NULL) {
-						RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
-						if (value.size() != lhs_c.wire->width)
-							log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
-						log("  Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
-						lhs_c.wire->attributes["\\init"] = value.as_const();
+				for (auto &lhs_c : lhs.chunks())
+				{
+					if (lhs_c.wire != nullptr)
+					{
+						SigSpec valuesig = rhs.extract(offset, lhs_c.width);
+						if (!valuesig.is_fully_const())
+							log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
+
+						Const value = valuesig.as_const();
+						Const &wireinit = lhs_c.wire->attributes["\\init"];
+
+						while (GetSize(wireinit.bits) < lhs_c.wire->width)
+							wireinit.bits.push_back(State::Sx);
+
+						for (int i = 0; i < lhs_c.width; i++) {
+							auto &initbit = wireinit.bits[i + lhs_c.offset];
+							if (initbit != State::Sx && initbit != value[i])
+								log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
+							initbit = value[i];
+						}
+
+						log("  Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
 					}
 					offset += lhs_c.width;
 				}
@@ -100,7 +115,7 @@ struct ProcInitPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_INIT pass (extract init attributes).\n");
+		log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
 
 		extra_args(args, 1, design);
 
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 943e8c562..dcfa212b5 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -391,7 +391,7 @@ struct ProcMuxPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
+		log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
 
 		extra_args(args, 1, design);
 
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index af17e8d38..5672fb475 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -76,7 +76,7 @@ struct ProcRmdeadPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
+		log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
 
 		extra_args(args, 1, design);