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-rw-r--r--passes/proc/proc_arst.cc50
-rw-r--r--passes/proc/proc_dff.cc196
-rw-r--r--passes/proc/proc_dlatch.cc50
-rw-r--r--passes/proc/proc_init.cc2
-rw-r--r--passes/proc/proc_mux.cc64
-rw-r--r--passes/proc/proc_prune.cc2
-rw-r--r--passes/proc/proc_rmdead.cc4
7 files changed, 184 insertions, 184 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index c606deb88..e400fcb72 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
- if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
+ if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
+ if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) {
- if (cell->getPort("\\A").is_fully_const()) {
- if (!cell->getPort("\\A").as_bool())
+ if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
+ if (cell->getPort(ID::A).is_fully_const()) {
+ if (!cell->getPort(ID::A).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\B"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
- if (cell->getPort("\\B").is_fully_const()) {
- if (!cell->getPort("\\B").as_bool())
+ if (cell->getPort(ID::B).is_fully_const()) {
+ if (!cell->getPort(ID::B).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
- if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) {
- if (cell->getPort("\\A").is_fully_const()) {
- if (cell->getPort("\\A").as_bool())
+ if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
+ if (cell->getPort(ID::A).is_fully_const()) {
+ if (cell->getPort(ID::A).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\B"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::B), ref, polarity);
}
- if (cell->getPort("\\B").is_fully_const()) {
- if (cell->getPort("\\B").as_bool())
+ if (cell->getPort(ID::B).is_fully_const()) {
+ if (cell->getPort(ID::B).as_bool())
polarity = !polarity;
- return check_signal(mod, cell->getPort("\\A"), ref, polarity);
+ return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
}
}
@@ -261,8 +261,8 @@ struct ProcArstPass : public Pass {
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks())
- if (chunk.wire && chunk.wire->attributes.count("\\init")) {
- RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
+ if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
+ RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
@@ -285,7 +285,7 @@ struct ProcArstPass : public Pass {
}
for (auto wire : delete_initattr_wires)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
} ProcArstPass;
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 519d35cd6..59cc5bd65 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -75,69 +75,69 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
log_abort();
if (sync_low_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_low_signals);
- cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
+ cell->setPort(ID::A, sync_low_signals);
+ cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
}
if (sync_low_signals.size() > 0) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_low_signals);
- cell->setPort("\\Y", mod->addWire(NEW_ID));
- sync_high_signals.append(cell->getPort("\\Y"));
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
+ cell->setPort(ID::A, sync_low_signals);
+ cell->setPort(ID::Y, mod->addWire(NEW_ID));
+ sync_high_signals.append(cell->getPort(ID::Y));
}
if (sync_high_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", sync_high_signals);
- cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
+ cell->setPort(ID::A, sync_high_signals);
+ cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
}
- RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
- inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
- inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
- inv_cell->setPort("\\A", sync_value);
- inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
-
- RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
- mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- mux_set_cell->setPort("\\A", sig_sr_set);
- mux_set_cell->setPort("\\B", sync_value);
- mux_set_cell->setPort("\\S", sync_high_signals);
- mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
-
- RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
- mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- mux_clr_cell->setPort("\\A", sig_sr_clr);
- mux_clr_cell->setPort("\\B", sync_value_inv);
- mux_clr_cell->setPort("\\S", sync_high_signals);
- mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
+ RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
+ inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
+ inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
+ inv_cell->setPort(ID::A, sync_value);
+ inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
+
+ RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
+ mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
+ mux_set_cell->setPort(ID::A, sig_sr_set);
+ mux_set_cell->setPort(ID::B, sync_value);
+ mux_set_cell->setPort(ID::S, sync_high_signals);
+ mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
+
+ RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
+ mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
+ mux_clr_cell->setPort(ID::A, sig_sr_clr);
+ mux_clr_cell->setPort(ID::B, sync_value_inv);
+ mux_clr_cell->setPort(ID::S, sync_high_signals);
+ mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
}
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
- cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
- cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
- cell->setPort("\\D", sig_d);
- cell->setPort("\\Q", sig_q);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\SET", sig_sr_set);
- cell->setPort("\\CLR", sig_sr_clr);
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
+ cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::SET, sig_sr_set);
+ cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -153,38 +153,38 @@ void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
- RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not");
- inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
- inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
- inv_set->setPort("\\A", sig_set);
- inv_set->setPort("\\Y", sig_set_inv);
-
- RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
- mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
- mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
- mux_sr_set->setPort("\\Y", sig_sr_set);
- mux_sr_set->setPort("\\S", set);
-
- RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
- mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
- mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
- mux_sr_clr->setPort("\\Y", sig_sr_clr);
- mux_sr_clr->setPort("\\S", set);
-
- RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
+ RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not));
+ inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size());
+ inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size());
+ inv_set->setPort(ID::A, sig_set);
+ inv_set->setPort(ID::Y, sig_set_inv);
+
+ RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux));
+ mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
+ mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
+ mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
+ mux_sr_set->setPort(ID::Y, sig_sr_set);
+ mux_sr_set->setPort(ID::S, set);
+
+ RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux));
+ mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
+ mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
+ mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
+ mux_sr_clr->setPort(ID::Y, sig_sr_clr);
+ mux_sr_clr->setPort(ID::S, set);
+
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
- cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
- cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
- cell->setPort("\\D", sig_in);
- cell->setPort("\\Q", sig_out);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\SET", sig_sr_set);
- cell->setPort("\\CLR", sig_sr_clr);
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
+ cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
+ cell->setPort(ID::D, sig_in);
+ cell->setPort(ID::Q, sig_out);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::SET, sig_sr_set);
+ cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@@ -196,24 +196,24 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? "$ff" : arst ? "$adff" : "$dff");
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
if (arst) {
- cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1);
- cell->parameters["\\ARST_VALUE"] = val_rst;
+ cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
+ cell->parameters[ID::ARST_VALUE] = val_rst;
}
if (!clk.empty()) {
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
}
- cell->setPort("\\D", sig_in);
- cell->setPort("\\Q", sig_out);
+ cell->setPort(ID::D, sig_in);
+ cell->setPort(ID::Q, sig_out);
if (arst)
- cell->setPort("\\ARST", *arst);
+ cell->setPort(ID::ARST, *arst);
if (!clk.empty())
- cell->setPort("\\CLK", clk);
+ cell->setPort(ID::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -303,15 +303,15 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
}
log_assert(inputs.size() == compare.size());
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
- cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- cell->setPort("\\A", inputs);
- cell->setPort("\\B", compare);
- cell->setPort("\\Y", sync_level->signal);
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
+ cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
+ cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
+ cell->setPort(ID::A, inputs);
+ cell->setPort(ID::B, compare);
+ cell->setPort(ID::Y, sync_level->signal);
many_async_rules.clear();
}
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index a0c8351b6..c9da1d1e3 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -42,16 +42,16 @@ struct proc_dlatch_db_t
{
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- auto sig_y = sigmap(cell->getPort("\\Y"));
+ auto sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++)
mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
pool<SigBit> mux_srcbits_pool;
- for (auto bit : sigmap(cell->getPort("\\A")))
+ for (auto bit : sigmap(cell->getPort(ID::A)))
mux_srcbits_pool.insert(bit);
- for (auto bit : sigmap(cell->getPort("\\B")))
+ for (auto bit : sigmap(cell->getPort(ID::B)))
mux_srcbits_pool.insert(bit);
vector<SigBit> mux_srcbits_vec;
@@ -180,9 +180,9 @@ struct proc_dlatch_db_t
Cell *cell = it->second.first;
int index = it->second.second;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
int width = GetSize(sig_a);
pool<int> children;
@@ -190,9 +190,9 @@ struct proc_dlatch_db_t
int n = find_mux_feedback(sig_a[index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_a[index] == needle) {
- SigSpec sig = cell->getPort("\\A");
+ SigSpec sig = cell->getPort(ID::A);
sig[index] = State::Sx;
- cell->setPort("\\A", sig);
+ cell->setPort(ID::A, sig);
}
for (int i = 0; i < GetSize(sig_s); i++)
n = make_inner(sig_s[i], State::S0, n);
@@ -203,9 +203,9 @@ struct proc_dlatch_db_t
n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == needle) {
- SigSpec sig = cell->getPort("\\B");
+ SigSpec sig = cell->getPort(ID::B);
sig[i*width + index] = State::Sx;
- cell->setPort("\\B", sig);
+ cell->setPort(ID::B, sig);
}
children.insert(make_inner(sig_s[i], State::S1, n));
}
@@ -257,9 +257,9 @@ struct proc_dlatch_db_t
void fixup_mux(Cell *cell)
{
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_b = cell->getPort("\\B");
- SigSpec sig_s = cell->getPort("\\S");
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
+ SigSpec sig_s = cell->getPort(ID::S);
SigSpec sig_any_valid_b;
SigSpec sig_new_b, sig_new_s;
@@ -278,18 +278,18 @@ struct proc_dlatch_db_t
}
if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
- cell->setPort("\\A", sig_any_valid_b);
+ cell->setPort(ID::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
- cell->type = "$mux";
- cell->unsetParam("\\S_WIDTH");
+ cell->type = ID($mux);
+ cell->unsetParam(ID::S_WIDTH);
} else {
- cell->type = "$pmux";
- cell->setParam("\\S_WIDTH", GetSize(sig_new_s));
+ cell->type = ID($pmux);
+ cell->setParam(ID::S_WIDTH, GetSize(sig_new_s));
}
- cell->setPort("\\B", sig_new_b);
- cell->setPort("\\S", sig_new_s);
+ cell->setPort(ID::B, sig_new_b);
+ cell->setPort(ID::S, sig_new_s);
}
void fixup_muxes()
@@ -317,7 +317,7 @@ struct proc_dlatch_db_t
pool<Cell*> next_queue;
for (auto cell : queue) {
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
fixup_mux(cell);
for (auto bit : upstream_cell2net[cell])
for (auto cell : upstream_net2cell[bit])
@@ -349,7 +349,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
continue;
}
- if (proc->get_bool_attribute(ID(always_ff)))
+ if (proc->get_bool_attribute(ID::always_ff))
log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n",
db.module->name.c_str(), proc->name.c_str());
@@ -387,7 +387,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
int offset = 0;
for (auto chunk : nolatches_bits.first.chunks()) {
SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width);
- if (proc->get_bool_attribute(ID(always_latch)))
+ if (proc->get_bool_attribute(ID::always_latch))
log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
@@ -418,7 +418,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
cell->set_src_attribute(src);
db.generated_dlatches.insert(cell);
- if (proc->get_bool_attribute(ID(always_comb)))
+ if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 462a384b7..dc00019aa 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -54,7 +54,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
Const value = valuesig.as_const();
- Const &wireinit = lhs_c.wire->attributes["\\init"];
+ Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index d029282fd..867ba1698 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -147,7 +147,7 @@ struct SnippetSwCache
void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
{
cell->attributes = sw->attributes;
- cell->add_strpool_attribute("\\src", cs->get_strpool_attribute("\\src"));
+ cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src));
}
RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
@@ -178,19 +178,19 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
else
{
// create compare cell
- RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq");
+ RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
apply_attrs(eq_cell, sw, cs);
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- eq_cell->setPort("\\A", sig);
- eq_cell->setPort("\\B", comp);
- eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
+ eq_cell->setPort(ID::A, sig);
+ eq_cell->setPort(ID::B, comp);
+ eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
@@ -204,15 +204,15 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
// reduce cmp vector to one logic signal
- RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
+ RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
apply_attrs(any_cell, sw, cs);
- any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
- any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
+ any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- any_cell->setPort("\\A", cmp_wire);
- any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire));
+ any_cell->setPort(ID::A, cmp_wire);
+ any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
@@ -239,14 +239,14 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
// create the multiplexer itself
- RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
+ RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
apply_attrs(mux_cell, sw, cs);
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
- mux_cell->setPort("\\A", else_signal);
- mux_cell->setPort("\\B", when_signal);
- mux_cell->setPort("\\S", ctrl_sig);
- mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire));
+ mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
+ mux_cell->setPort(ID::A, else_signal);
+ mux_cell->setPort(ID::B, when_signal);
+ mux_cell->setPort(ID::S, ctrl_sig);
+ mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
@@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
- log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
+ log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
- if (when_signal == last_mux_cell->getPort("\\A"))
+ if (when_signal == last_mux_cell->getPort(ID::A))
return;
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
- last_mux_cell->type = "$pmux";
+ last_mux_cell->type = ID($pmux);
- RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S");
+ RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
new_s.append(ctrl_sig);
- last_mux_cell->setPort("\\S", new_s);
+ last_mux_cell->setPort(ID::S, new_s);
- RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B");
+ RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
new_b.append(when_signal);
- last_mux_cell->setPort("\\B", new_b);
+ last_mux_cell->setPort(ID::B, new_b);
- last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
+ last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
@@ -281,7 +281,7 @@ const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRul
{
pool<SigBit> bits;
- if (sw->get_bool_attribute("\\full_case"))
+ if (sw->get_bool_attribute(ID::full_case))
{
bool first_case = true;
@@ -337,7 +337,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
std::vector<int> pgroups(sw->cases.size());
bool is_simple_parallel_case = true;
- if (!sw->get_bool_attribute("\\parallel_case")) {
+ if (!sw->get_bool_attribute(ID::parallel_case)) {
if (!swpara.count(sw)) {
pool<Const> case_values;
for (size_t i = 0; i < sw->cases.size(); i++) {
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index caf938a74..8d11447f6 100644
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -38,7 +38,7 @@ struct PruneWorker
pool<RTLIL::SigBit> do_switch(RTLIL::SwitchRule *sw, pool<RTLIL::SigBit> assigned, pool<RTLIL::SigBit> &affected)
{
pool<RTLIL::SigBit> all_assigned;
- bool full_case = sw->get_bool_attribute("\\full_case");
+ bool full_case = sw->get_bool_attribute(ID::full_case);
bool first = true;
for (auto it : sw->cases) {
if (it->compare.empty())
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index 4f40be446..6afaf25d1 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -62,8 +62,8 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter)
pool.take_all();
}
- if (pool.empty() && !sw->get_bool_attribute("\\full_case")) {
- sw->set_bool_attribute("\\full_case");
+ if (pool.empty() && !sw->get_bool_attribute(ID::full_case)) {
+ sw->set_bool_attribute(ID::full_case);
full_case_counter++;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 07:08:41 +0000