1 files changed, 190 insertions, 146 deletions

diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 6fc480925..46c76eba9 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -19,6 +19,8 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/ffinit.h"
+#include "kernel/ff.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -39,8 +41,6 @@ struct Async2syncPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
-		log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n");
-		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -62,169 +62,213 @@ struct Async2syncPass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
-			dict<SigBit, State> initbits;
-			pool<SigBit> del_initbits;
-
-			for (auto wire : module->wires())
-				if (wire->attributes.count(ID::init) > 0)
-				{
-					Const initval = wire->attributes.at(ID::init);
-					SigSpec initsig = sigmap(wire);
-
-					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
-						if (initval[i] == State::S0 || initval[i] == State::S1)
-							initbits[initsig[i]] = initval[i];
-				}
+			FfInitVals initvals(&sigmap, module);
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in(ID($adff)))
-				{
-					// bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
-					bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool();
-					Const arst_val = cell->parameters[ID::ARST_VALUE];
-
-					// SigSpec sig_clk = cell->getPort(ID::CLK);
-					SigSpec sig_arst = cell->getPort(ID::ARST);
-					SigSpec sig_d = cell->getPort(ID::D);
-					SigSpec sig_q = cell->getPort(ID::Q);
-
-					log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
-							log_id(module), log_id(cell), log_id(cell->type),
-							log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q));
-
-					Const init_val;
-					for (int i = 0; i < GetSize(sig_q); i++) {
-						SigBit bit = sigmap(sig_q[i]);
-						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
-						del_initbits.insert(bit);
-					}
-
-					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
-					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes[ID::init] = init_val;
+				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+					continue;
 
-					if (arst_pol) {
-						module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
-						module->addMux(NEW_ID, new_q, arst_val, sig_arst, sig_q);
-					} else {
-						module->addMux(NEW_ID, arst_val, sig_d, sig_arst, new_d);
-						module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
-					}
+				FfData ff(&initvals, cell);
 
-					cell->setPort(ID::D, new_d);
-					cell->setPort(ID::Q, new_q);
-					cell->unsetPort(ID::ARST);
-					cell->unsetParam(ID::ARST_POLARITY);
-					cell->unsetParam(ID::ARST_VALUE);
-					cell->type = ID($dff);
+				// Skip for $_FF_ and $ff cells.
+				if (ff.has_gclk)
 					continue;
-				}
 
-				if (cell->type.in(ID($dffsr)))
+				if (ff.has_clk)
 				{
-					// bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
-					bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool();
-					bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool();
-
-					// SigSpec sig_clk = cell->getPort(ID::CLK);
-					SigSpec sig_set = cell->getPort(ID::SET);
-					SigSpec sig_clr = cell->getPort(ID::CLR);
-					SigSpec sig_d = cell->getPort(ID::D);
-					SigSpec sig_q = cell->getPort(ID::Q);
-
-					log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
-							log_id(module), log_id(cell), log_id(cell->type),
-							log_signal(sig_set), log_signal(sig_clr), log_signal(sig_d), log_signal(sig_q));
-
-					Const init_val;
-					for (int i = 0; i < GetSize(sig_q); i++) {
-						SigBit bit = sigmap(sig_q[i]);
-						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
-						del_initbits.insert(bit);
+					if (ff.has_sr) {
+						ff.unmap_ce_srst();
+
+						log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_d), log_signal(ff.sig_q));
+
+						initvals.remove_init(ff.sig_q);
+
+						Wire *new_d = module->addWire(NEW_ID, ff.width);
+						Wire *new_q = module->addWire(NEW_ID, ff.width);
+
+						SigSpec sig_set = ff.sig_set;
+						SigSpec sig_clr = ff.sig_clr;
+
+						if (!ff.pol_set) {
+							if (!ff.is_fine)
+								sig_set = module->Not(NEW_ID, sig_set);
+							else
+								sig_set = module->NotGate(NEW_ID, sig_set);
+						}
+
+						if (ff.pol_clr) {
+							if (!ff.is_fine)
+								sig_clr = module->Not(NEW_ID, sig_clr);
+							else
+								sig_clr = module->NotGate(NEW_ID, sig_clr);
+						}
+
+						if (!ff.is_fine) {
+							SigSpec tmp = module->Or(NEW_ID, ff.sig_d, sig_set);
+							module->addAnd(NEW_ID, tmp, sig_clr, new_d);
+
+							tmp = module->Or(NEW_ID, new_q, sig_set);
+							module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q);
+						} else {
+							SigSpec tmp = module->OrGate(NEW_ID, ff.sig_d, sig_set);
+							module->addAndGate(NEW_ID, tmp, sig_clr, new_d);
+
+							tmp = module->OrGate(NEW_ID, new_q, sig_set);
+							module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q);
+						}
+
+						ff.sig_d = new_d;
+						ff.sig_q = new_q;
+						ff.has_sr = false;
+					} else if (ff.has_aload) {
+						ff.unmap_ce_srst();
+
+						log("Replacing %s.%s (%s): ALOAD=%s, AD=%s, D=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_d), log_signal(ff.sig_q));
+
+						initvals.remove_init(ff.sig_q);
+
+						Wire *new_d = module->addWire(NEW_ID, ff.width);
+						Wire *new_q = module->addWire(NEW_ID, ff.width);
+
+						if (ff.pol_aload) {
+							if (!ff.is_fine) {
+								module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
+								module->addMux(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
+							} else {
+								module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q);
+								module->addMuxGate(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d);
+							}
+						} else {
+							if (!ff.is_fine) {
+								module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
+								module->addMux(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
+							} else {
+								module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q);
+								module->addMuxGate(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d);
+							}
+						}
+
+						ff.sig_d = new_d;
+						ff.sig_q = new_q;
+						ff.has_aload = false;
+					} else if (ff.has_arst) {
+						ff.unmap_srst();
+
+						log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_arst), log_signal(ff.sig_d), log_signal(ff.sig_q));
+
+						initvals.remove_init(ff.sig_q);
+
+						Wire *new_q = module->addWire(NEW_ID, ff.width);
+
+						if (ff.pol_arst) {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q);
+							else
+								module->addMuxGate(NEW_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q);
+						} else {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q);
+							else
+								module->addMuxGate(NEW_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q);
+						}
+
+						ff.sig_q = new_q;
+						ff.has_arst = false;
+						ff.has_srst = true;
+						ff.ce_over_srst = false;
+						ff.val_srst = ff.val_arst;
+						ff.sig_srst = ff.sig_arst;
+						ff.pol_srst = ff.pol_arst;
+					} else {
+						continue;
 					}
-
-					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
-					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes[ID::init] = init_val;
-
-					if (!set_pol)
-						sig_set = module->Not(NEW_ID, sig_set);
-
-					if (clr_pol)
-						sig_clr = module->Not(NEW_ID, sig_clr);
-
-					SigSpec tmp = module->Or(NEW_ID, sig_d, sig_set);
-					module->addAnd(NEW_ID, tmp, sig_clr, new_d);
-
-					tmp = module->Or(NEW_ID, new_q, sig_set);
-					module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
-
-					cell->setPort(ID::D, new_d);
-					cell->setPort(ID::Q, new_q);
-					cell->unsetPort(ID::SET);
-					cell->unsetPort(ID::CLR);
-					cell->unsetParam(ID::SET_POLARITY);
-					cell->unsetParam(ID::CLR_POLARITY);
-					cell->type = ID($dff);
-					continue;
 				}
-
-				if (cell->type.in(ID($dlatch)))
+				else
 				{
-					bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool();
-
-					SigSpec sig_en = cell->getPort(ID::EN);
-					SigSpec sig_d = cell->getPort(ID::D);
-					SigSpec sig_q = cell->getPort(ID::Q);
-
+					// Latch.
 					log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
 							log_id(module), log_id(cell), log_id(cell->type),
-							log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
-
-					Const init_val;
-					for (int i = 0; i < GetSize(sig_q); i++) {
-						SigBit bit = sigmap(sig_q[i]);
-						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
-						del_initbits.insert(bit);
+							log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+
+					initvals.remove_init(ff.sig_q);
+
+					Wire *new_q = module->addWire(NEW_ID, ff.width);
+					Wire *new_d;
+
+					if (ff.has_aload) {
+						new_d = module->addWire(NEW_ID, ff.width);
+						if (ff.pol_aload) {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
+							else
+								module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);
+						} else {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
+							else
+								module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d);
+						}
+					} else {
+						new_d = new_q;
 					}
 
-					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
-					new_q->attributes[ID::init] = init_val;
-
-					if (en_pol) {
-						module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
+					if (ff.has_sr) {
+						SigSpec sig_set = ff.sig_set;
+						SigSpec sig_clr = ff.sig_clr;
+
+						if (!ff.pol_set) {
+							if (!ff.is_fine)
+								sig_set = module->Not(NEW_ID, sig_set);
+							else
+								sig_set = module->NotGate(NEW_ID, sig_set);
+						}
+
+						if (ff.pol_clr) {
+							if (!ff.is_fine)
+								sig_clr = module->Not(NEW_ID, sig_clr);
+							else
+								sig_clr = module->NotGate(NEW_ID, sig_clr);
+						}
+
+						if (!ff.is_fine) {
+							SigSpec tmp = module->Or(NEW_ID, new_d, sig_set);
+							module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q);
+						} else {
+							SigSpec tmp = module->OrGate(NEW_ID, new_d, sig_set);
+							module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q);
+						}
+					} else if (ff.has_arst) {
+						if (ff.pol_arst) {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q);
+							else
+								module->addMuxGate(NEW_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q);
+						} else {
+							if (!ff.is_fine)
+								module->addMux(NEW_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q);
+							else
+								module->addMuxGate(NEW_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q);
+						}
 					} else {
-						module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
+						module->connect(ff.sig_q, new_d);
 					}
 
-					cell->setPort(ID::D, sig_q);
-					cell->setPort(ID::Q, new_q);
-					cell->unsetPort(ID::EN);
-					cell->unsetParam(ID::EN_POLARITY);
-					cell->type = ID($ff);
-					continue;
+					ff.sig_d = new_d;
+					ff.sig_q = new_q;
+					ff.has_aload = false;
+					ff.has_arst = false;
+					ff.has_sr = false;
+					ff.has_gclk = true;
 				}
+				ff.emit();
 			}
-
-			for (auto wire : module->wires())
-				if (wire->attributes.count(ID::init) > 0)
-				{
-					bool delete_initattr = true;
-					Const initval = wire->attributes.at(ID::init);
-					SigSpec initsig = sigmap(wire);
-
-					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
-						if (del_initbits.count(initsig[i]) > 0)
-							initval[i] = State::Sx;
-						else if (initval[i] != State::Sx)
-							delete_initattr = false;
-
-					if (delete_initattr)
-						wire->attributes.erase(ID::init);
-					else
-						wire->attributes.at(ID::init) = initval;
-				}
 		}
 	}
 } Async2syncPass;