1 files changed, 115 insertions, 6 deletions

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index ef6d5dd72..4bb4aa047 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Clk2fflogicPass : public Pass {
 	Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass {
 		log("multiple clocks.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		// bool flag_noinit = false;
 
@@ -72,7 +72,88 @@ struct Clk2fflogicPass : public Pass {
 
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				if (cell->type.in("$dlatch"))
+				if (cell->type.in("$mem"))
+				{
+					int abits = cell->getParam("\\ABITS").as_int();
+					int width = cell->getParam("\\WIDTH").as_int();
+					int rd_ports = cell->getParam("\\RD_PORTS").as_int();
+					int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+
+					for (int i = 0; i < rd_ports; i++) {
+						if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+							log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
+									"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
+					}
+
+					Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
+					Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+
+					SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
+					SigSpec wr_en_port = cell->getPort("\\WR_EN");
+					SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
+					SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+
+					for (int wport = 0; wport < wr_ports; wport++)
+					{
+						bool clken = wr_clk_en_param[wport] == State::S1;
+						bool clkpol = wr_clk_pol_param[wport] == State::S1;
+
+						if (!clken)
+							continue;
+
+						SigBit clk = wr_clk_port[wport];
+						SigSpec en = wr_en_port.extract(wport*width, width);
+						SigSpec addr = wr_addr_port.extract(wport*abits, abits);
+						SigSpec data = wr_data_port.extract(wport*width, width);
+
+						log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n",
+								wport, log_id(module), log_id(cell), log_signal(clk),
+								log_signal(addr), log_signal(data));
+
+						Wire *past_clk = module->addWire(NEW_ID);
+						past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+						module->addFf(NEW_ID, clk, past_clk);
+
+						SigSpec clock_edge_pattern;
+
+						if (clkpol) {
+							clock_edge_pattern.append_bit(State::S0);
+							clock_edge_pattern.append_bit(State::S1);
+						} else {
+							clock_edge_pattern.append_bit(State::S1);
+							clock_edge_pattern.append_bit(State::S0);
+						}
+
+						SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
+
+						SigSpec en_q = module->addWire(NEW_ID, GetSize(en));
+						module->addFf(NEW_ID, en, en_q);
+
+						SigSpec addr_q = module->addWire(NEW_ID, GetSize(addr));
+						module->addFf(NEW_ID, addr, addr_q);
+
+						SigSpec data_q = module->addWire(NEW_ID, GetSize(data));
+						module->addFf(NEW_ID, data, data_q);
+
+						wr_clk_port[wport] = State::S0;
+						wr_en_port.replace(wport*width, module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge));
+						wr_addr_port.replace(wport*abits, addr_q);
+						wr_data_port.replace(wport*width, data_q);
+
+						wr_clk_en_param[wport] = State::S0;
+						wr_clk_pol_param[wport] = State::S0;
+					}
+
+					cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
+					cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+
+					cell->setPort("\\WR_CLK", wr_clk_port);
+					cell->setPort("\\WR_EN", wr_en_port);
+					cell->setPort("\\WR_ADDR", wr_addr_port);
+					cell->setPort("\\WR_DATA", wr_data_port);
+				}
+
+				if (cell->type.in("$dlatch", "$dlatchsr"))
 				{
 					bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
 
@@ -87,10 +168,31 @@ struct Clk2fflogicPass : public Pass {
 					Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
 					module->addFf(NEW_ID, sig_q, past_q);
 
-					if (enpol)
-						module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
+					if (cell->type == "$dlatch")
+					{
+						if (enpol)
+							module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
+						else
+							module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q);
+					}
 					else
-						module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q);
+					{
+						SigSpec t;
+						if (enpol)
+							t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
+						else
+							t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
+
+						SigSpec s = cell->getPort("\\SET");
+						if (!cell->parameters["\\SET_POLARITY"].as_bool())
+							s = module->Not(NEW_ID, s);
+						t = module->Or(NEW_ID, t, s);
+
+						SigSpec c = cell->getPort("\\CLR");
+						if (cell->parameters["\\CLR_POLARITY"].as_bool())
+							c = module->Not(NEW_ID, c);
+						module->addAnd(NEW_ID, t, c, sig_q);
+					}
 
 					Const initval;
 					bool assign_initval = false;
@@ -151,6 +253,13 @@ struct Clk2fflogicPass : public Pass {
 						SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
 						Const rstval = cell->parameters["\\ARST_VALUE"];
 
+						Wire *past_arst = module->addWire(NEW_ID);
+						module->addFf(NEW_ID, arst, past_arst);
+						if (cell->parameters["\\ARST_POLARITY"].as_bool())
+							arst = module->LogicOr(NEW_ID, arst, past_arst);
+						else
+							arst = module->LogicAnd(NEW_ID, arst, past_arst);
+
 						if (cell->parameters["\\ARST_POLARITY"].as_bool())
 							module->addMux(NEW_ID, qval, rstval, arst, sig_q);
 						else