aboutsummaryrefslogtreecommitdiffstats
path: root/passes/sat/clk2fflogic.cc
diff options
context:
space:
mode:
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
-rw-r--r--passes/sat/clk2fflogic.cc94
1 files changed, 55 insertions, 39 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 062083972..b1b0567a0 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -39,8 +39,14 @@ struct Clk2fflogicPass : public Pass {
log("multiple clocks.\n");
log("\n");
}
- SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity) {
- Wire *past_sig = module->addWire(NEW_ID, GetSize(sig));
+ SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, bool is_fine, IdString past_sig_id) {
+ if (!is_fine)
+ return wrap_async_control(module, sig, polarity, past_sig_id);
+ return wrap_async_control_gate(module, sig, polarity, past_sig_id);
+ }
+ SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
+ Wire *past_sig = module->addWire(past_sig_id, GetSize(sig));
+ past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig));
module->addFf(NEW_ID, sig, past_sig);
if (polarity)
sig = module->Or(NEW_ID, sig, past_sig);
@@ -51,8 +57,9 @@ struct Clk2fflogicPass : public Pass {
else
return module->Not(NEW_ID, sig);
}
- SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) {
- Wire *past_sig = module->addWire(NEW_ID);
+ SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) {
+ Wire *past_sig = module->addWire(past_sig_id);
+ past_sig->attributes[ID::init] = polarity ? State::S0 : State::S1;
module->addFfGate(NEW_ID, sig, past_sig);
if (polarity)
sig = module->OrGate(NEW_ID, sig, past_sig);
@@ -105,7 +112,7 @@ struct Clk2fflogicPass : public Pass {
i, log_id(module), log_id(mem.memid), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
- Wire *past_clk = module->addWire(NEW_ID);
+ Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", log_id(mem.memid), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
@@ -121,13 +128,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
- SigSpec en_q = module->addWire(NEW_ID, GetSize(port.en));
+ SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", log_id(mem.memid), i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
- SigSpec addr_q = module->addWire(NEW_ID, GetSize(port.addr));
+ SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", log_id(mem.memid), i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
- SigSpec data_q = module->addWire(NEW_ID, GetSize(port.data));
+ SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", log_id(mem.memid), i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
port.clk = State::S0;
@@ -148,12 +155,36 @@ struct Clk2fflogicPass : public Pass {
if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
FfData ff(&initvals, cell);
- if (ff.has_d && !ff.has_clk && !ff.has_en) {
+ if (ff.has_gclk) {
// Already a $ff or $_FF_ cell.
continue;
}
- Wire *past_q = module->addWire(NEW_ID, ff.width);
+ if (ff.has_clk) {
+ log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
+ log_id(module), log_id(cell), log_id(cell->type),
+ log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
+ } else if (ff.has_aload) {
+ log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+ log_id(module), log_id(cell), log_id(cell->type),
+ log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+ } else {
+ // $sr.
+ log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
+ log_id(module), log_id(cell), log_id(cell->type),
+ log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
+ }
+
+ ff.remove();
+
+ // Strip spaces from signal name, since Yosys IDs can't contain spaces
+ // Spaces only occur when we have a signal that's a slice of a larger bus,
+ // e.g. "\myreg [5:0]", so removing spaces shouldn't result in loss of uniqueness
+ std::string sig_q_str = log_signal(ff.sig_q);
+ sig_q_str.erase(std::remove(sig_q_str.begin(), sig_q_str.end(), ' '), sig_q_str.end());
+
+ Wire *past_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_q_wire", sig_q_str.c_str())), ff.width);
+
if (!ff.is_fine) {
module->addFf(NEW_ID, ff.sig_q, past_q);
} else {
@@ -163,9 +194,9 @@ struct Clk2fflogicPass : public Pass {
initvals.set_init(past_q, ff.val_init);
if (ff.has_clk) {
- ff.unmap_ce_srst(module);
+ ff.unmap_ce_srst();
- Wire *past_clk = module->addWire(NEW_ID);
+ Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_clk#%s", sig_q_str.c_str(), log_signal(ff.sig_clk))));
initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
if (!ff.is_fine)
@@ -173,10 +204,6 @@ struct Clk2fflogicPass : public Pass {
else
module->addFfGate(NEW_ID, ff.sig_clk, past_clk);
- log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
- log_id(module), log_id(cell), log_id(cell->type),
- log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
-
SigSpec clock_edge_pattern;
if (ff.pol_clk) {
@@ -189,7 +216,7 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {ff.sig_clk, SigSpec(past_clk)}, clock_edge_pattern);
- Wire *past_d = module->addWire(NEW_ID, ff.width);
+ Wire *past_d = module->addWire(NEW_ID_SUFFIX(stringf("%s#past_d_wire", sig_q_str.c_str())), ff.width);
if (!ff.is_fine)
module->addFf(NEW_ID, ff.sig_d, past_d);
else
@@ -202,30 +229,22 @@ struct Clk2fflogicPass : public Pass {
qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
else
qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
- } else if (ff.has_d) {
-
- log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
- log_id(module), log_id(cell), log_id(cell->type),
- log_signal(ff.sig_en), log_signal(ff.sig_d), log_signal(ff.sig_q));
+ } else {
+ qval = past_q;
+ }
- SigSpec sig_en = wrap_async_control(module, ff.sig_en, ff.pol_en);
+ if (ff.has_aload) {
+ SigSpec sig_aload = wrap_async_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine, NEW_ID);
if (!ff.is_fine)
- qval = module->Mux(NEW_ID, past_q, ff.sig_d, sig_en);
+ qval = module->Mux(NEW_ID, qval, ff.sig_ad, sig_aload);
else
- qval = module->MuxGate(NEW_ID, past_q, ff.sig_d, sig_en);
- } else {
-
- log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
- log_id(module), log_id(cell), log_id(cell->type),
- log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
-
- qval = past_q;
+ qval = module->MuxGate(NEW_ID, qval, ff.sig_ad, sig_aload);
}
if (ff.has_sr) {
- SigSpec setval = wrap_async_control(module, ff.sig_set, ff.pol_set);
- SigSpec clrval = wrap_async_control(module, ff.sig_clr, ff.pol_clr);
+ SigSpec setval = wrap_async_control(module, ff.sig_set, ff.pol_set, ff.is_fine, NEW_ID);
+ SigSpec clrval = wrap_async_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine, NEW_ID);
if (!ff.is_fine) {
clrval = module->Not(NEW_ID, clrval);
qval = module->Or(NEW_ID, qval, setval);
@@ -236,7 +255,8 @@ struct Clk2fflogicPass : public Pass {
module->addAndGate(NEW_ID, qval, clrval, ff.sig_q);
}
} else if (ff.has_arst) {
- SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst);
+ IdString id = NEW_ID_SUFFIX(stringf("%s#past_arst#%s", sig_q_str.c_str(), log_signal(ff.sig_arst)));
+ SigSpec arst = wrap_async_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine, id);
if (!ff.is_fine)
module->addMux(NEW_ID, qval, ff.val_arst, arst, ff.sig_q);
else
@@ -244,10 +264,6 @@ struct Clk2fflogicPass : public Pass {
} else {
module->connect(ff.sig_q, qval);
}
-
- initvals.remove_init(ff.sig_q);
- module->remove(cell);
- continue;
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 12:15:49 +0000