diff options
Diffstat (limited to 'passes/sat/freduce.cc')
| -rw-r--r-- | passes/sat/freduce.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 54016e528..5dfd7bd3f 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -635,8 +635,8 @@ struct FreduceWorker batches.push_back(outputs); bits_full_total += outputs.size(); } - if (inv_mode && cell->type == "$_NOT_") - inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y")))); + if (inv_mode && cell->type == ID($_NOT_)) + inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y)))); } int bits_count = 0; @@ -731,9 +731,9 @@ struct FreduceWorker { inv_sig = module->addWire(NEW_ID); - RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_"); - inv_cell->setPort("\\A", grp[0].bit); - inv_cell->setPort("\\Y", inv_sig); + RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_)); + inv_cell->setPort(ID::A, grp[0].bit); + inv_cell->setPort(ID::Y, inv_sig); } module->connect(RTLIL::SigSig(grp[i].bit, inv_sig)); |