1 files changed, 539 insertions, 196 deletions

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index a7c109374..d15ae9b57 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -22,6 +22,7 @@
 #include "kernel/celltypes.h"
 #include "kernel/mem.h"
 #include "kernel/fstdata.h"
+#include "kernel/ff.h"
 
 #include <ctime>
 
@@ -64,6 +65,15 @@ static double stringToTime(std::string str)
 	return value * pow(10.0, g_units.at(endptr));
 }
 
+struct SimWorker;
+struct OutputWriter
+{
+	OutputWriter(SimWorker *w) { worker = w;};
+	virtual ~OutputWriter() {};
+	virtual void write(std::map<int, bool> &use_signal) = 0;
+	SimWorker *worker;
+};
+
 struct SimShared
 {
 	bool debug = false;
@@ -76,6 +86,9 @@ struct SimShared
 	double stop_time = -1;
 	SimulationMode sim_mode = SimulationMode::sim;
 	bool cycles_set = false;
+	std::vector<std::unique_ptr<OutputWriter>> outputfiles;
+	std::vector<std::pair<int,std::map<int,Const>>> output_data;
+	bool ignore_x = false;
 };
 
 void zinit(State &v)
@@ -113,8 +126,13 @@ struct SimInstance
 
 	struct ff_state_t
 	{
-		State past_clock;
 		Const past_d;
+		Const past_ad;
+		State past_clk;
+		State past_ce;
+		State past_srst;
+		
+		FfData data;
 	};
 
 	struct mem_state_t
@@ -134,8 +152,7 @@ struct SimInstance
 
 	std::vector<Mem> memories;
 
-	dict<Wire*, pair<int, Const>> vcd_database;
-	dict<Wire*, pair<fstHandle, Const>> fst_database;
+	dict<Wire*, pair<int, Const>> signal_database;
 	dict<Wire*, fstHandle> fst_handles;
 
 	SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
@@ -209,10 +226,15 @@ struct SimInstance
 					}
 			}
 
-			if (cell->type.in(ID($dff))) {
+			if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+				FfData ff_data(nullptr, cell);
 				ff_state_t ff;
-				ff.past_clock = State::Sx;
-				ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
+				ff.past_d = Const(State::Sx, ff_data.width);
+				ff.past_ad = Const(State::Sx, ff_data.width);
+				ff.past_clk = State::Sx;
+				ff.past_ce = State::Sx;
+				ff.past_srst = State::Sx;
+				ff.data = ff_data;
 				ff_database[cell] = ff;
 			}
 
@@ -229,11 +251,10 @@ struct SimInstance
 		{
 			for (auto &it : ff_database)
 			{
-				Cell *cell = it.first;
 				ff_state_t &ff = it.second;
 				zinit(ff.past_d);
 
-				SigSpec qsig = cell->getPort(ID::Q);
+				SigSpec qsig = it.second.data.sig_q;
 				Const qdata = get_state(qsig);
 				zinit(qdata);
 				set_state(qsig, qdata);
@@ -466,21 +487,62 @@ struct SimInstance
 
 		for (auto &it : ff_database)
 		{
-			Cell *cell = it.first;
 			ff_state_t &ff = it.second;
-
-			if (cell->type.in(ID($dff)))
-			{
-				bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
-				State current_clock = get_state(cell->getPort(ID::CLK))[0];
-
-				if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
-						(ff.past_clock == State::S0 || current_clock != State::S0))
-					continue;
-
-				if (set_state(cell->getPort(ID::Q), ff.past_d))
-					did_something = true;
+			FfData &ff_data = ff.data;
+
+			Const current_q = get_state(ff.data.sig_q);
+
+			if (ff_data.has_clk) {
+				// flip-flops
+				State current_clk = get_state(ff_data.sig_clk)[0];
+				if (ff_data.pol_clk ? (ff.past_clk == State::S0 && current_clk != State::S0) :
+							(ff.past_clk == State::S1 && current_clk != State::S1)) {
+					bool ce = ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0);
+					// set if no ce, or ce is enabled
+					if (!ff_data.has_ce || (ff_data.has_ce && ce)) {
+						current_q = ff.past_d;
+					}
+					// override if sync reset
+					if ((ff_data.has_srst) && (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0)) &&
+						((!ff_data.ce_over_srst) || (ff_data.ce_over_srst && ce))) {
+						current_q = ff_data.val_srst;
+					}
+				}
+			}
+			// async load
+			if (ff_data.has_aload) {
+				State current_aload = get_state(ff_data.sig_aload)[0];
+				if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
+					current_q = ff_data.has_clk ? ff.past_ad : get_state(ff.data.sig_ad);
+				}
+			}
+			// async reset
+			if (ff_data.has_arst) {
+				State current_arst = get_state(ff_data.sig_arst)[0];
+				if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
+					current_q = ff_data.val_arst;
+				}
 			}
+			// handle set/reset
+			if (ff.data.has_sr) {
+				Const current_clr = get_state(ff.data.sig_clr);
+				Const current_set = get_state(ff.data.sig_set);
+
+				for(int i=0;i<ff.past_d.size();i++) {
+					if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
+						current_q[i] = State::S0;
+					}
+					else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
+						current_q[i] = State::S1;
+					}
+				}
+			}
+			if (ff_data.has_gclk) {
+				// $ff
+				current_q = ff.past_d;
+			}
+			if (set_state(ff_data.sig_q, current_q))
+				did_something = true;
 		}
 
 		for (auto &it : mem_database)
@@ -538,13 +600,22 @@ struct SimInstance
 	{
 		for (auto &it : ff_database)
 		{
-			Cell *cell = it.first;
 			ff_state_t &ff = it.second;
 
-			if (cell->type.in(ID($dff))) {
-				ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
-				ff.past_d = get_state(cell->getPort(ID::D));
-			}
+			if (ff.data.has_aload)
+				ff.past_ad = get_state(ff.data.sig_ad);
+
+			if (ff.data.has_clk || ff.data.has_gclk)
+				ff.past_d = get_state(ff.data.sig_d);
+
+			if (ff.data.has_clk)
+				ff.past_clk = get_state(ff.data.sig_clk)[0];
+
+			if (ff.data.has_ce)
+				ff.past_ce = get_state(ff.data.sig_ce)[0];
+
+			if (ff.data.has_srst)
+				ff.past_srst = get_state(ff.data.sig_srst)[0];
 		}
 
 		for (auto &it : mem_database)
@@ -595,8 +666,7 @@ struct SimInstance
 
 		for (auto &it : ff_database)
 		{
-			Cell *cell = it.first;
-			SigSpec sig_q = cell->getPort(ID::Q);
+			SigSpec sig_q = it.second.data.sig_q;
 			Const initval = get_state(sig_q);
 
 			for (int i = 0; i < GetSize(sig_q); i++)
@@ -626,130 +696,94 @@ struct SimInstance
 			it.second->writeback(wbmods);
 	}
 
-	void write_vcd_header(std::ofstream &f, int &id)
+	void register_signals(int &id)
 	{
-		f << stringf("$scope module %s $end\n", log_id(name()));
-
 		for (auto wire : module->wires())
 		{
 			if (shared->hide_internal && wire->name[0] == '$')
 				continue;
 
-			f << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
-			vcd_database[wire] = make_pair(id++, Const());
+			signal_database[wire] = make_pair(id, Const());
+			id++;
 		}
 
 		for (auto child : children)
-			child.second->write_vcd_header(f, id);
-
-		f << stringf("$upscope $end\n");
+			child.second->register_signals(id);
 	}
 
-	void write_vcd_step(std::ofstream &f)
+	void write_output_header(std::function<void(IdString)> enter_scope, std::function<void()> exit_scope, std::function<void(Wire*, int)> register_signal)
 	{
-		for (auto &it : vcd_database)
-		{
-			Wire *wire = it.first;
-			Const value = get_state(wire);
-			int id = it.second.first;
-
-			if (it.second.second == value)
-				continue;
-
-			it.second.second = value;
-
-			f << "b";
-			for (int i = GetSize(value)-1; i >= 0; i--) {
-				switch (value[i]) {
-					case State::S0: f << "0"; break;
-					case State::S1: f << "1"; break;
-					case State::Sx: f << "x"; break;
-					default: f << "z";
-				}
-			}
-
-			f << stringf(" n%d\n", id);
-		}
-
-		for (auto child : children)
-			child.second->write_vcd_step(f);
-	}
+		enter_scope(name());
 
-	void write_fst_header(struct fstContext *f)
-	{
-		fstWriterSetScope(f, FST_ST_VCD_MODULE, stringf("%s",log_id(name())).c_str(), nullptr);
-		for (auto wire : module->wires())
+		for (auto signal : signal_database)
 		{
-			if (shared->hide_internal && wire->name[0] == '$')
-				continue;
-
-			fstHandle id = fstWriterCreateVar(f, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
-												stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
-			fst_database[wire] = make_pair(id, Const());
+			register_signal(signal.first, signal.second.first);
 		}
 
 		for (auto child : children)
-			child.second->write_fst_header(f);
+			child.second->write_output_header(enter_scope, exit_scope, register_signal);
 
-		fstWriterSetUpscope(f);
+		exit_scope();
 	}
 
-	void write_fst_step(struct fstContext *f)
+	void register_output_step_values(std::map<int,Const> *data)
 	{
-		for (auto &it : fst_database)
+		for (auto &it : signal_database)
 		{
 			Wire *wire = it.first;
 			Const value = get_state(wire);
-			fstHandle id = it.second.first;
+			int id = it.second.first;
 
 			if (it.second.second == value)
 				continue;
 
 			it.second.second = value;
-			std::stringstream ss;
-			for (int i = GetSize(value)-1; i >= 0; i--) {
-				switch (value[i]) {
-					case State::S0: ss << "0"; break;
-					case State::S1: ss << "1"; break;
-					case State::Sx: ss << "x"; break;
-					default: ss << "z";
-				}
-			}
-			fstWriterEmitValueChange(f, id, ss.str().c_str());
+			data->emplace(id, value);
 		}
 
 		for (auto child : children)
-			child.second->write_fst_step(f);
+			child.second->register_output_step_values(data);
 	}
 
-	void setInitState(uint64_t time)
+	void setInitState()
 	{
 		for (auto &it : ff_database)
 		{
-			Cell *cell = it.first;
-			
-			SigSpec qsig = cell->getPort(ID::Q);
+			SigSpec qsig = it.second.data.sig_q;
 			if (qsig.is_wire()) {
 				IdString name = qsig.as_wire()->name;
 				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
 				if (id==0 && name.isPublic())
 					log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
 				if (id!=0) {
-					Const fst_val = Const::from_string(shared->fst->valueAt(id, time));
+					Const fst_val = Const::from_string(shared->fst->valueOf(id));
 					set_state(qsig, fst_val);
 				}
 			}
 		}
 		for (auto child : children)
-			child.second->setInitState(time);
+			child.second->setInitState();
 	}
 
-	bool checkSignals(uint64_t time)
+	void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
+	{
+		for(auto bit : bits) {
+			if (bit.first >= GetSize(values))
+				log_error("Too few input data bits in file.\n");
+			switch(values.at(bit.first)) {
+				case '0': set_state(bit.second.first, bit.second.second ? State::S1 : State::S0); break;
+				case '1': set_state(bit.second.first, bit.second.second ? State::S0 : State::S1); break;
+				default: set_state(bit.second.first, State::Sx); break;
+			}
+		}
+	}
+
+	bool checkSignals()
 	{
 		bool retVal = false;
 		for(auto &item : fst_handles) {
 			if (item.second==0) continue; // Ignore signals not found
-			Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
+			Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
 			Const sim_val = get_state(item.first);
 			if (sim_val.size()!=fst_val.size())
 				log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
@@ -779,7 +813,7 @@ struct SimInstance
 			}
 		}
 		for (auto child : children)
-			retVal |= child.second->checkSignals(time);
+			retVal |= child.second->checkSignals();
 		return retVal;
 	}
 };
@@ -787,84 +821,49 @@ struct SimInstance
 struct SimWorker : SimShared
 {
 	SimInstance *top = nullptr;
-	std::ofstream vcdfile;
-	struct fstContext *fstfile = nullptr;
 	pool<IdString> clock, clockn, reset, resetn;
 	std::string timescale;
 	std::string sim_filename;
+	std::string map_filename;
 	std::string scope;
 
 	~SimWorker()
 	{
+		outputfiles.clear();
 		delete top;
 	}
 
-	void write_vcd_header()
+	void register_signals()
 	{
-		vcdfile << stringf("$version %s $end\n", yosys_version_str);
-
-		std::time_t t = std::time(nullptr);
-		char mbstr[255];
-		if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
-			vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
-		}
-
-		if (!timescale.empty())
-			vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
-
 		int id = 1;
-		top->write_vcd_header(vcdfile, id);
-
-		vcdfile << stringf("$enddefinitions $end\n");
-	}
-
-	void write_vcd_step(int t)
-	{
-		vcdfile << stringf("#%d\n", t);
-		top->write_vcd_step(vcdfile);
-	}
-
-	void write_fst_header()
-	{
-		std::time_t t = std::time(nullptr);
-		fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
-		fstWriterSetVersion(fstfile, yosys_version_str);
-		if (!timescale.empty())
-			fstWriterSetTimescaleFromString(fstfile, timescale.c_str());
-
-		fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
-		fstWriterSetRepackOnClose(fstfile, 1);
-	   
-		top->write_fst_header(fstfile);
+		top->register_signals(id);
 	}
 
-	void write_fst_step(int t)
+	void register_output_step(int t)
 	{
-		fstWriterEmitTimeChange(fstfile, t);
-
-		top->write_fst_step(fstfile);
-	}
-
-	void write_output_header()
-	{
-		if (vcdfile.is_open())
-			write_vcd_header();
-		if (fstfile)
-			write_fst_header();
-	}
-
-	void write_output_step(int t)
-	{
-		if (vcdfile.is_open())
-			write_vcd_step(t);
-		if (fstfile)
-			write_fst_step(t);
+		std::map<int,Const> data;
+		top->register_output_step_values(&data);
+		output_data.emplace_back(t, data);
 	}
 
-	void write_output_end()
+	void write_output_files()
 	{
-		if (fstfile)
-			fstWriterClose(fstfile);
+		std::map<int, bool> use_signal;
+		bool first = ignore_x;
+		for(auto& d : output_data)
+		{
+			if (first) {
+				for (auto &data : d.second)
+					use_signal[data.first] = !data.second.is_fully_undef();
+				first = false;
+			} else {
+				for (auto &data : d.second)
+					use_signal[data.first] = true;
+			}
+			if (!ignore_x) break;
+		}
+		for(auto& writer : outputfiles)
+			writer->write(use_signal);
 	}
 
 	void update()
@@ -906,6 +905,7 @@ struct SimWorker : SimShared
 	{
 		log_assert(top == nullptr);
 		top = new SimInstance(this, scope, topmod);
+		register_signals();
 
 		if (debug)
 			log("\n===== 0 =====\n");
@@ -920,8 +920,7 @@ struct SimWorker : SimShared
 
 		update();
 
-		write_output_header();
-		write_output_step(0);
+		register_output_step(0);
 
 		for (int cycle = 0; cycle < numcycles; cycle++)
 		{
@@ -933,7 +932,7 @@ struct SimWorker : SimShared
 			set_inports(clockn, State::S1);
 
 			update();
-			write_output_step(10*cycle + 5);
+			register_output_step(10*cycle + 5);
 
 			if (debug)
 				log("\n===== %d =====\n", 10*cycle + 10);
@@ -949,12 +948,12 @@ struct SimWorker : SimShared
 			}
 
 			update();
-			write_output_step(10*cycle + 10);
+			register_output_step(10*cycle + 10);
 		}
 
-		write_output_step(10*numcycles + 2);
+		register_output_step(10*numcycles + 2);
 
-		write_output_end();
+		write_output_files();
 
 		if (writeback) {
 			pool<Module*> wbmods;
@@ -971,6 +970,7 @@ struct SimWorker : SimShared
 			log_error("Scope must be defined for co-simulation.\n");
 
 		top = new SimInstance(this, scope, topmod);
+		register_signals();
 
 		std::vector<fstHandle> fst_clock;
 
@@ -998,8 +998,6 @@ struct SimWorker : SimShared
 				log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
 			fst_clock.push_back(id);
 		}
-		if (fst_clock.size()==0)
-			log_error("No clock signals defined for input file\n");
 
 		SigMap sigmap(topmod);
 		std::map<Wire*,fstHandle> inputs;
@@ -1044,42 +1042,358 @@ struct SimWorker : SimShared
 		if (stopCount<startCount) {
 			log_error("Stop time is before start time\n");
 		}
-		auto samples = fst->getAllEdges(fst_clock, startCount, stopCount);
 
-		// Limit to number of cycles if provided
-		if (cycles_set && ((size_t)(numcycles *2) < samples.size()))
-			samples.erase(samples.begin() + (numcycles*2), samples.end());
-
-		// Add setup time (start time)
-		if (samples.empty() || samples.front()!=startCount)
-			samples.insert(samples.begin(), startCount);
-
-		fst->reconstructAllAtTimes(samples);
 		bool initial = true;
 		int cycle = 0;
-		log("Co-simulation from %lu%s to %lu%s\n", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
-		for(auto &time : samples) {
-			log("Co-simulating cycle %d [%lu%s].\n", cycle, (unsigned long)time, fst->getTimescaleString());
-			for(auto &item : inputs) {
-				std::string v = fst->valueAt(item.second, time);
-				top->set_state(item.first, Const::from_string(v));
-			}
-			if (initial) {
-				top->setInitState(time);
-				initial = false;
-			}
-			update();
+		log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
+		if (cycles_set) 
+			log(" for %d clock cycle(s)",numcycles);
+		log("\n");
+		bool all_samples = fst_clock.empty();
+
+		try {
+			fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
+				log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
+				bool did_something = false;
+				for(auto &item : inputs) {
+					std::string v = fst->valueOf(item.second);
+					did_something |= top->set_state(item.first, Const::from_string(v));
+				}
 
-			bool status = top->checkSignals(time);
-			if (status)
-				log_error("Signal difference\n");
-			cycle++;
+				if (initial) {
+					top->setInitState();
+					initial = false;
+				}
+				if (did_something)
+					update();
+				register_output_step(time);
+
+				bool status = top->checkSignals();
+				if (status)
+					log_error("Signal difference\n");
+				cycle++;
+
+				// Limit to number of cycles if provided
+				if (cycles_set && cycle > numcycles *2)
+					throw fst_end_of_data_exception();
+				if (time==stopCount)
+					throw fst_end_of_data_exception();
+			});
+		} catch(fst_end_of_data_exception) {
+			// end of data detected
 		}
+
+		write_output_files();
+
 		if (writeback) {
 			pool<Module*> wbmods;
 			top->writeback(wbmods);
 		}
+		delete fst;
 	}
+
+	void run_cosim_witness(Module *topmod)
+	{
+		log_assert(top == nullptr);
+		std::ifstream mf(map_filename);
+		std::string type, symbol;
+		int variable, index;
+		dict<int, std::pair<SigBit,bool>> inputs, inits, latches;
+		while (mf >> type >> variable >> index >> symbol) {
+			RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
+			Wire *w = topmod->wire(escaped_s);
+			if (!w)
+				log_error("Wire %s not present in module %s\n",log_signal(w),log_id(topmod));
+			if (index < w->start_offset || index > w->start_offset + w->width)
+				log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
+			if (type == "input") {
+				inputs[variable] = {SigBit(w,index), false};
+			} else if (type == "init") {
+				inits[variable] = {SigBit(w,index), false};
+			} else if (type == "latch") {
+				latches[variable] = {SigBit(w,index), false};
+			} else if (type == "invlatch") {
+				latches[variable] = {SigBit(w,index), true};
+			}
+		}
+
+		std::ifstream f;
+		f.open(sim_filename.c_str());
+		if (f.fail() || GetSize(sim_filename) == 0)
+			log_error("Can not open file `%s`\n", sim_filename.c_str());
+
+		int state = 0;
+		std::string status;
+		int cycle = 0;
+		top = new SimInstance(this, scope, topmod);
+		register_signals();
+
+		while (!f.eof())
+		{
+			std::string line;
+			std::getline(f, line);
+			if (line.size()==0 || line[0]=='#') continue;
+			if (line[0]=='.') break;
+			if (state==0 && line.size()!=1) {
+				// old format detected, latch data
+				state = 2;
+			}
+			if (state==1 && line[0]!='b' && line[0]!='c') {
+				// was old format but with 1 bit latch
+				top->setState(latches, status);
+				state = 3;
+			}
+
+			switch(state)
+			{
+				case 0:
+					status = line;
+					state = 1;
+					break;
+				case 1:
+					state = 2;
+					break;
+				case 2:
+					top->setState(latches, line);
+					state = 3;
+					break;
+				default:
+					log("Simulating cycle %d.\n", cycle);
+					top->setState(inputs, line);
+					if (cycle) {
+						set_inports(clock, State::S1);
+						set_inports(clockn, State::S0);
+					} else {
+						top->setState(inits, line);
+						set_inports(clock, State::S0);
+						set_inports(clockn, State::S1);
+					}
+					update();
+					register_output_step(10*cycle);
+					if (cycle) {
+						set_inports(clock, State::S0);
+						set_inports(clockn, State::S1);
+						update();
+						register_output_step(10*cycle + 5);
+					}
+					cycle++;
+					break;
+			}
+		}
+		register_output_step(10*cycle);
+		write_output_files();
+	}
+};
+
+struct VCDWriter : public OutputWriter
+{
+	VCDWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
+		vcdfile.open(filename.c_str());
+	}
+
+	void write(std::map<int, bool> &use_signal) override
+	{
+		if (!vcdfile.is_open()) return;
+		vcdfile << stringf("$version %s $end\n", yosys_version_str);
+
+		std::time_t t = std::time(nullptr);
+		char mbstr[255];
+		if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
+			vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
+		}
+
+		if (!worker->timescale.empty())
+			vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
+
+		worker->top->write_output_header(
+			[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
+			[this]() { vcdfile << stringf("$upscope $end\n");},
+			[this,use_signal](Wire *wire, int id) { if (use_signal.at(id)) vcdfile << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire)); }
+		);
+
+		vcdfile << stringf("$enddefinitions $end\n");
+
+		for(auto& d : worker->output_data)
+		{
+			vcdfile << stringf("#%d\n", d.first);
+			for (auto &data : d.second)
+			{
+				if (!use_signal.at(data.first)) continue;
+				Const value = data.second;
+				vcdfile << "b";
+				for (int i = GetSize(value)-1; i >= 0; i--) {
+					switch (value[i]) {
+						case State::S0: vcdfile << "0"; break;
+						case State::S1: vcdfile << "1"; break;
+						case State::Sx: vcdfile << "x"; break;
+						default: vcdfile << "z";
+					}
+				}
+				vcdfile << stringf(" n%d\n", data.first);
+			}
+		}
+	}
+
+	std::ofstream vcdfile;
+};
+
+struct FSTWriter : public OutputWriter
+{
+	FSTWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
+		fstfile = (struct fstContext *)fstWriterCreate(filename.c_str(),1);
+	}
+
+	virtual ~FSTWriter()
+	{
+		fstWriterClose(fstfile);
+	}
+
+	void write(std::map<int, bool> &use_signal) override
+	{
+		if (!fstfile) return;
+		std::time_t t = std::time(nullptr);
+		fstWriterSetDate(fstfile, asctime(std::localtime(&t)));
+		fstWriterSetVersion(fstfile, yosys_version_str);
+		if (!worker->timescale.empty())
+			fstWriterSetTimescaleFromString(fstfile, worker->timescale.c_str());
+
+		fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
+		fstWriterSetRepackOnClose(fstfile, 1);
+	   
+	   	worker->top->write_output_header(
+			[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
+			[this]() { fstWriterSetUpscope(fstfile); },
+			[this,use_signal](Wire *wire, int id) {
+				if (!use_signal.at(id)) return;
+				fstHandle fst_id = fstWriterCreateVar(fstfile, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
+												stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
+
+				mapping.emplace(id, fst_id);
+			}
+		);
+
+		for(auto& d : worker->output_data)
+		{
+			fstWriterEmitTimeChange(fstfile, d.first);
+			for (auto &data : d.second)
+			{
+				if (!use_signal.at(data.first)) continue;
+				Const value = data.second;
+				std::stringstream ss;
+				for (int i = GetSize(value)-1; i >= 0; i--) {
+					switch (value[i]) {
+						case State::S0: ss << "0"; break;
+						case State::S1: ss << "1"; break;
+						case State::Sx: ss << "x"; break;
+						default: ss << "z";
+					}
+				}
+				fstWriterEmitValueChange(fstfile, mapping[data.first], ss.str().c_str());
+			}
+		}
+	}
+
+	struct fstContext *fstfile = nullptr;
+	std::map<int,fstHandle> mapping;
+};
+
+struct AIWWriter : public OutputWriter
+{
+	AIWWriter(SimWorker *worker, std::string filename) : OutputWriter(worker) {
+		aiwfile.open(filename.c_str());
+	}
+
+	virtual ~AIWWriter()
+	{
+		aiwfile << '.' << '\n';
+	}
+
+	void write(std::map<int, bool> &) override
+	{
+		if (!aiwfile.is_open()) return;
+		std::ifstream mf(worker->map_filename);
+		std::string type, symbol;
+		int variable, index;
+		while (mf >> type >> variable >> index >> symbol) {
+			RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
+			Wire *w = worker->top->module->wire(escaped_s);
+			if (!w)
+				log_error("Wire %s not present in module %s\n",log_signal(w),log_id(worker->top->module));
+			if (index < w->start_offset || index > w->start_offset + w->width)
+				log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
+			if (type == "input") {
+				aiw_inputs[variable] = SigBit(w,index);
+			} else if (type == "init") {
+				aiw_inits[variable] = SigBit(w,index);
+			} else if (type == "latch") {
+				aiw_latches[variable] = {SigBit(w,index), false};
+			} else if (type == "invlatch") {
+				aiw_latches[variable] = {SigBit(w,index), true};
+			}
+		}
+
+		worker->top->write_output_header(
+			[](IdString) {},
+			[]() {},
+			[this](Wire *wire, int id) { mapping[wire] = id; }
+		);
+
+		std::map<int, Yosys::RTLIL::Const> current;
+		bool first = true;
+		for(auto& d : worker->output_data)
+		{
+			for (auto &data : d.second)
+			{
+				current[data.first] = data.second;
+			}
+			if (first) {
+				for (int i = 0;; i++)
+				{
+					if (aiw_latches.count(i)) {
+						SigBit bit = aiw_latches.at(i).first;
+						auto v = current[mapping[bit.wire]].bits.at(bit.offset);
+						if (v == State::S1)
+							aiwfile << (aiw_latches.at(i).second ? '0' : '1');
+						else
+							aiwfile << (aiw_latches.at(i).second ? '1' : '0');
+						continue;
+					}
+					aiwfile << '\n';
+					break;
+				}
+				first = false;
+			}
+
+			for (int i = 0;; i++)
+			{
+				if (aiw_inputs.count(i)) {
+					SigBit bit = aiw_inputs.at(i);
+					auto v = current[mapping[bit.wire]].bits.at(bit.offset);
+					if (v == State::S1)
+						aiwfile << '1';
+					else
+						aiwfile << '0';
+					continue;
+				}
+				if (aiw_inits.count(i)) {
+					SigBit bit = aiw_inits.at(i);
+					auto v = current[mapping[bit.wire]].bits.at(bit.offset);
+					if (v == State::S1)
+						aiwfile << '1';
+					else
+						aiwfile << '0';
+					continue;
+				}
+				aiwfile << '\n';
+				break;
+			}
+		} 
+	}
+
+	std::ofstream aiwfile;
+	dict<int, std::pair<SigBit, bool>> aiw_latches;
+	dict<int, SigBit> aiw_inputs, aiw_inits;
+	std::map<Wire*,int> mapping;
 };
 
 struct SimPass : public Pass {
@@ -1098,6 +1412,13 @@ struct SimPass : public Pass {
 		log("    -fst <filename>\n");
 		log("        write the simulation results to the given FST file\n");
 		log("\n");
+		log("    -aiw <filename>\n");
+		log("        write the simulation results to an AIGER witness file\n");
+		log("        (requires a *.aim file via -map)\n");
+		log("\n");
+		log("    -x\n");
+		log("        ignore constant x outputs in simulation file.\n");
+		log("\n");
 		log("    -clock <portname>\n");
 		log("        name of top-level clock input\n");
 		log("\n");
@@ -1131,6 +1452,9 @@ struct SimPass : public Pass {
 		log("    -r\n");
 		log("        read simulation results file (file formats supported: FST)\n");
 		log("\n");
+		log("    -map <filename>\n");
+		log("        read file with port and latch symbols, needed for AIGER witness input\n");
+		log("\n");
 		log("    -scope\n");
 		log("        scope of simulation top model\n");
 		log("\n");
@@ -1172,13 +1496,19 @@ struct SimPass : public Pass {
 			if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
 				std::string vcd_filename = args[++argidx];
 				rewrite_filename(vcd_filename);
-				worker.vcdfile.open(vcd_filename.c_str());
+				worker.outputfiles.emplace_back(std::unique_ptr<VCDWriter>(new VCDWriter(&worker, vcd_filename.c_str())));
 				continue;
 			}
 			if (args[argidx] == "-fst" && argidx+1 < args.size()) {
 				std::string fst_filename = args[++argidx];
 				rewrite_filename(fst_filename);
-				worker.fstfile = (struct fstContext *)fstWriterCreate(fst_filename.c_str(),1);
+				worker.outputfiles.emplace_back(std::unique_ptr<FSTWriter>(new FSTWriter(&worker, fst_filename.c_str())));
+				continue;
+			}
+			if (args[argidx] == "-aiw" && argidx+1 < args.size()) {
+				std::string aiw_filename = args[++argidx];
+				rewrite_filename(aiw_filename);
+				worker.outputfiles.emplace_back(std::unique_ptr<AIWWriter>(new AIWWriter(&worker, aiw_filename.c_str())));
 				continue;
 			}
 			if (args[argidx] == "-n" && argidx+1 < args.size()) {
@@ -1232,6 +1562,12 @@ struct SimPass : public Pass {
 				worker.sim_filename = sim_filename;
 				continue;
 			}
+			if (args[argidx] == "-map" && argidx+1 < args.size()) {
+				std::string map_filename = args[++argidx];
+				rewrite_filename(map_filename);
+				worker.map_filename = map_filename;
+				continue;
+			}
 			if (args[argidx] == "-scope" && argidx+1 < args.size()) {
 				worker.scope = args[++argidx];
 				continue;
@@ -1268,6 +1604,10 @@ struct SimPass : public Pass {
 				worker.sim_mode = SimulationMode::gate;
 				continue;
 			}
+			if (args[argidx] == "-x") {
+				worker.ignore_x = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -1293,7 +1633,10 @@ struct SimPass : public Pass {
 		if (worker.sim_filename.empty())
 			worker.run(top_mod, numcycles);
 		else
-			worker.run_cosim(top_mod, numcycles);
+			if (worker.map_filename.empty())
+				worker.run_cosim(top_mod, numcycles);
+			else
+				worker.run_cosim_witness(top_mod);
 	}
 } SimPass;