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-rw-r--r--passes/sat/assertpmux.cc30
-rw-r--r--passes/sat/async2sync.cc98
-rw-r--r--passes/sat/clk2fflogic.cc134
-rw-r--r--passes/sat/cutpoint.cc2
-rw-r--r--passes/sat/eval.cc90
-rw-r--r--passes/sat/expose.cc223
-rw-r--r--passes/sat/fmcombine.cc14
-rw-r--r--passes/sat/fminit.cc4
-rw-r--r--passes/sat/freduce.cc34
-rw-r--r--passes/sat/miter.cc238
-rw-r--r--passes/sat/mutate.cc6
-rw-r--r--passes/sat/sat.cc16
-rw-r--r--passes/sat/sim.cc136
13 files changed, 499 insertions, 526 deletions
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 3b432c461..5bf2296ab 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -52,14 +52,14 @@ struct AssertpmuxWorker
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- int width = cell->getParam("\\WIDTH").as_int();
- int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1;
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
- SigSpec sig_a = sigmap(cell->getPort("\\A"));
- SigSpec sig_b = sigmap(cell->getPort("\\B"));
- SigSpec sig_s = sigmap(cell->getPort("\\S"));
+ SigSpec sig_a = sigmap(cell->getPort(ID::A));
+ SigSpec sig_b = sigmap(cell->getPort(ID::B));
+ SigSpec sig_s = sigmap(cell->getPort(ID::S));
for (int i = 0; i < numports; i++) {
SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width);
@@ -98,12 +98,12 @@ struct AssertpmuxWorker
if (muxport_actsignal.count(muxport) == 0) {
if (portidx == 0)
- muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S"));
+ muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S));
else
- muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1];
+ muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1];
}
- output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx])));
+ output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
}
output.sort_and_unify();
@@ -148,10 +148,10 @@ struct AssertpmuxWorker
{
log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
- int swidth = pmux->getParam("\\S_WIDTH").as_int();
+ int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1);
- SigSpec sel = pmux->getPort("\\S");
+ SigSpec sel = pmux->getPort(ID::S);
SigSpec cnt(State::S0, cntbits);
for (int i = 0; i < swidth; i++)
@@ -164,7 +164,7 @@ struct AssertpmuxWorker
assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID)));
if (!flag_always)
- assert_en.append(get_activation(pmux->getPort("\\Y")));
+ assert_en.append(get_activation(pmux->getPort(ID::Y)));
if (GetSize(assert_en) == 0)
assert_en = State::S1;
@@ -174,8 +174,8 @@ struct AssertpmuxWorker
Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en);
- if (pmux->attributes.count("\\src") != 0)
- assert_cell->attributes["\\src"] = pmux->attributes.at("\\src");
+ if (pmux->attributes.count(ID::src) != 0)
+ assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src);
}
};
@@ -227,7 +227,7 @@ struct AssertpmuxPass : public Pass {
vector<Cell*> pmux_cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$pmux")
+ if (cell->type == ID($pmux))
pmux_cells.push_back(cell);
for (auto cell : pmux_cells)
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 740248545..e344e2b5b 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -66,9 +66,9 @@ struct Async2syncPass : public Pass {
pool<SigBit> del_initbits;
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -78,16 +78,16 @@ struct Async2syncPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type.in("$adff"))
+ if (cell->type.in(ID($adff)))
{
- // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
- bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
- Const arst_val = cell->parameters["\\ARST_VALUE"];
+ // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool();
+ Const arst_val = cell->parameters[ID::ARST_VALUE];
- // SigSpec sig_clk = cell->getPort("\\CLK");
- SigSpec sig_arst = cell->getPort("\\ARST");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ // SigSpec sig_clk = cell->getPort(ID::CLK);
+ SigSpec sig_arst = cell->getPort(ID::ARST);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
@@ -102,7 +102,7 @@ struct Async2syncPass : public Pass {
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (arst_pol) {
module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
@@ -112,26 +112,26 @@ struct Async2syncPass : public Pass {
module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
}
- cell->setPort("\\D", new_d);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\ARST");
- cell->unsetParam("\\ARST_POLARITY");
- cell->unsetParam("\\ARST_VALUE");
- cell->type = "$dff";
+ cell->setPort(ID::D, new_d);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::ARST);
+ cell->unsetParam(ID::ARST_POLARITY);
+ cell->unsetParam(ID::ARST_VALUE);
+ cell->type = ID($dff);
continue;
}
- if (cell->type.in("$dffsr"))
+ if (cell->type.in(ID($dffsr)))
{
- // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
- bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool();
- bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool();
+ // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool();
+ bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool();
- // SigSpec sig_clk = cell->getPort("\\CLK");
- SigSpec sig_set = cell->getPort("\\SET");
- SigSpec sig_clr = cell->getPort("\\CLR");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ // SigSpec sig_clk = cell->getPort(ID::CLK);
+ SigSpec sig_set = cell->getPort(ID::SET);
+ SigSpec sig_clr = cell->getPort(ID::CLR);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
@@ -146,7 +146,7 @@ struct Async2syncPass : public Pass {
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (!set_pol)
sig_set = module->Not(NEW_ID, sig_set);
@@ -160,23 +160,23 @@ struct Async2syncPass : public Pass {
tmp = module->Or(NEW_ID, new_q, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
- cell->setPort("\\D", new_d);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\SET");
- cell->unsetPort("\\CLR");
- cell->unsetParam("\\SET_POLARITY");
- cell->unsetParam("\\CLR_POLARITY");
- cell->type = "$dff";
+ cell->setPort(ID::D, new_d);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->type = ID($dff);
continue;
}
- if (cell->type.in("$dlatch"))
+ if (cell->type.in(ID($dlatch)))
{
- bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
+ bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool();
- SigSpec sig_en = cell->getPort("\\EN");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_en = cell->getPort(ID::EN);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
@@ -190,7 +190,7 @@ struct Async2syncPass : public Pass {
}
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (en_pol) {
module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
@@ -198,20 +198,20 @@ struct Async2syncPass : public Pass {
module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
}
- cell->setPort("\\D", sig_q);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\EN");
- cell->unsetParam("\\EN_POLARITY");
- cell->type = "$ff";
+ cell->setPort(ID::D, sig_q);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::EN);
+ cell->unsetParam(ID::EN_POLARITY);
+ cell->type = ID($ff);
continue;
}
}
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -221,9 +221,9 @@ struct Async2syncPass : public Pass {
delete_initattr = false;
if (delete_initattr)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at("\\init") = initval;
+ wire->attributes.at(ID::init) = initval;
}
}
}
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index f9e7783a9..1e155e52c 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -60,9 +60,9 @@ struct Clk2fflogicPass : public Pass {
pool<SigBit> del_initbits;
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -72,26 +72,26 @@ struct Clk2fflogicPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type.in("$mem"))
+ if (cell->type.in(ID($mem)))
{
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
for (int i = 0; i < rd_ports; i++) {
- if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
}
- Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
- Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+ Const wr_clk_en_param = cell->getParam(ID::WR_CLK_ENABLE);
+ Const wr_clk_pol_param = cell->getParam(ID::WR_CLK_POLARITY);
- SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
- SigSpec wr_en_port = cell->getPort("\\WR_EN");
- SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
- SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+ SigSpec wr_clk_port = cell->getPort(ID::WR_CLK);
+ SigSpec wr_en_port = cell->getPort(ID::WR_EN);
+ SigSpec wr_addr_port = cell->getPort(ID::WR_ADDR);
+ SigSpec wr_data_port = cell->getPort(ID::WR_DATA);
for (int wport = 0; wport < wr_ports; wport++)
{
@@ -111,17 +111,17 @@ struct Clk2fflogicPass : public Pass {
log_signal(addr), log_signal(data));
Wire *past_clk = module->addWire(NEW_ID);
- past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+ past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
module->addFf(NEW_ID, clk, past_clk);
SigSpec clock_edge_pattern;
if (clkpol) {
- clock_edge_pattern.append_bit(State::S0);
- clock_edge_pattern.append_bit(State::S1);
+ clock_edge_pattern.append(State::S0);
+ clock_edge_pattern.append(State::S1);
} else {
- clock_edge_pattern.append_bit(State::S1);
- clock_edge_pattern.append_bit(State::S0);
+ clock_edge_pattern.append(State::S1);
+ clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
@@ -144,22 +144,22 @@ struct Clk2fflogicPass : public Pass {
wr_clk_pol_param[wport] = State::S0;
}
- cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
- cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+ cell->setParam(ID::WR_CLK_ENABLE, wr_clk_en_param);
+ cell->setParam(ID::WR_CLK_POLARITY, wr_clk_pol_param);
- cell->setPort("\\WR_CLK", wr_clk_port);
- cell->setPort("\\WR_EN", wr_en_port);
- cell->setPort("\\WR_ADDR", wr_addr_port);
- cell->setPort("\\WR_DATA", wr_data_port);
+ cell->setPort(ID::WR_CLK, wr_clk_port);
+ cell->setPort(ID::WR_EN, wr_en_port);
+ cell->setPort(ID::WR_ADDR, wr_addr_port);
+ cell->setPort(ID::WR_DATA, wr_data_port);
}
- if (cell->type.in("$dlatch", "$dlatchsr"))
+ if (cell->type.in(ID($dlatch), ID($dlatchsr)))
{
- bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
+ bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
- SigSpec sig_en = cell->getPort("\\EN");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_en = cell->getPort(ID::EN);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
@@ -168,7 +168,7 @@ struct Clk2fflogicPass : public Pass {
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_q, past_q);
- if (cell->type == "$dlatch")
+ if (cell->type == ID($dlatch))
{
if (enpol)
module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
@@ -183,13 +183,13 @@ struct Clk2fflogicPass : public Pass {
else
t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
- SigSpec s = cell->getPort("\\SET");
- if (!cell->parameters["\\SET_POLARITY"].as_bool())
+ SigSpec s = cell->getPort(ID::SET);
+ if (!cell->parameters[ID::SET_POLARITY].as_bool())
s = module->Not(NEW_ID, s);
t = module->Or(NEW_ID, t, s);
- SigSpec c = cell->getPort("\\CLR");
- if (cell->parameters["\\CLR_POLARITY"].as_bool())
+ SigSpec c = cell->getPort(ID::CLR);
+ if (cell->parameters[ID::CLR_POLARITY].as_bool())
c = module->Not(NEW_ID, c);
module->addAnd(NEW_ID, t, c, sig_q);
}
@@ -208,13 +208,13 @@ struct Clk2fflogicPass : public Pass {
}
if (assign_initval)
- past_q->attributes["\\init"] = initval;
+ past_q->attributes[ID::init] = initval;
module->remove(cell);
continue;
}
- bool word_dff = cell->type.in("$dff", "$adff", "$dffsr");
+ bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr));
if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
@@ -224,8 +224,8 @@ struct Clk2fflogicPass : public Pass {
bool clkpol;
SigSpec clk;
if (word_dff) {
- clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
- clk = cell->getPort("\\CLK");
+ clkpol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ clk = cell->getPort(ID::CLK);
}
else {
if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
@@ -236,19 +236,19 @@ struct Clk2fflogicPass : public Pass {
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
clkpol = cell->type[8] == 'P';
else log_abort();
- clk = cell->getPort("\\C");
+ clk = cell->getPort(ID::C);
}
Wire *past_clk = module->addWire(NEW_ID);
- past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+ past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
if (word_dff)
module->addFf(NEW_ID, clk, past_clk);
else
module->addFfGate(NEW_ID, clk, past_clk);
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
@@ -257,11 +257,11 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge_pattern;
if (clkpol) {
- clock_edge_pattern.append_bit(State::S0);
- clock_edge_pattern.append_bit(State::S1);
+ clock_edge_pattern.append(State::S0);
+ clock_edge_pattern.append(State::S1);
} else {
- clock_edge_pattern.append_bit(State::S1);
- clock_edge_pattern.append_bit(State::S0);
+ clock_edge_pattern.append(State::S1);
+ clock_edge_pattern.append(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
@@ -277,20 +277,20 @@ struct Clk2fflogicPass : public Pass {
module->addFfGate(NEW_ID, sig_q, past_q);
}
- if (cell->type == "$adff")
+ if (cell->type == ID($adff))
{
- SigSpec arst = cell->getPort("\\ARST");
+ SigSpec arst = cell->getPort(ID::ARST);
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
- Const rstval = cell->parameters["\\ARST_VALUE"];
+ Const rstval = cell->parameters[ID::ARST_VALUE];
Wire *past_arst = module->addWire(NEW_ID);
module->addFf(NEW_ID, arst, past_arst);
- if (cell->parameters["\\ARST_POLARITY"].as_bool())
+ if (cell->parameters[ID::ARST_POLARITY].as_bool())
arst = module->LogicOr(NEW_ID, arst, past_arst);
else
arst = module->LogicAnd(NEW_ID, arst, past_arst);
- if (cell->parameters["\\ARST_POLARITY"].as_bool())
+ if (cell->parameters[ID::ARST_POLARITY].as_bool())
module->addMux(NEW_ID, qval, rstval, arst, sig_q);
else
module->addMux(NEW_ID, rstval, qval, arst, sig_q);
@@ -299,7 +299,7 @@ struct Clk2fflogicPass : public Pass {
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
{
- SigSpec arst = cell->getPort("\\R");
+ SigSpec arst = cell->getPort(ID::R);
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigBit rstval = (cell->type[8] == '1');
@@ -316,16 +316,16 @@ struct Clk2fflogicPass : public Pass {
module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
}
else
- if (cell->type == "$dffsr")
+ if (cell->type == ID($dffsr))
{
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
- SigSpec setval = cell->getPort("\\SET");
- SigSpec clrval = cell->getPort("\\CLR");
+ SigSpec setval = cell->getPort(ID::SET);
+ SigSpec clrval = cell->getPort(ID::CLR);
- if (!cell->parameters["\\SET_POLARITY"].as_bool())
+ if (!cell->parameters[ID::SET_POLARITY].as_bool())
setval = module->Not(NEW_ID, setval);
- if (cell->parameters["\\CLR_POLARITY"].as_bool())
+ if (cell->parameters[ID::CLR_POLARITY].as_bool())
clrval = module->Not(NEW_ID, clrval);
qval = module->Or(NEW_ID, qval, setval);
@@ -336,8 +336,8 @@ struct Clk2fflogicPass : public Pass {
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
{
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
- SigSpec setval = cell->getPort("\\S");
- SigSpec clrval = cell->getPort("\\R");
+ SigSpec setval = cell->getPort(ID::S);
+ SigSpec clrval = cell->getPort(ID::R);
if (cell->type[9] != 'P')
setval = module->Not(NEW_ID, setval);
@@ -348,7 +348,7 @@ struct Clk2fflogicPass : public Pass {
qval = module->OrGate(NEW_ID, qval, setval);
module->addAndGate(NEW_ID, qval, clrval, sig_q);
}
- else if (cell->type == "$dff")
+ else if (cell->type == ID($dff))
{
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
}
@@ -371,8 +371,8 @@ struct Clk2fflogicPass : public Pass {
}
if (assign_initval) {
- past_d->attributes["\\init"] = initval;
- past_q->attributes["\\init"] = initval;
+ past_d->attributes[ID::init] = initval;
+ past_q->attributes[ID::init] = initval;
}
module->remove(cell);
@@ -381,10 +381,10 @@ struct Clk2fflogicPass : public Pass {
}
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@@ -394,9 +394,9 @@ struct Clk2fflogicPass : public Pass {
delete_initattr = false;
if (delete_initattr)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at("\\init") = initval;
+ wire->attributes.at(ID::init) = initval;
}
}
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index b4549bc39..26cc69211 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -75,7 +75,7 @@ struct CutpointPass : public Pass {
pool<SigBit> cutpoint_bits;
for (auto cell : module->selected_cells()) {
- if (cell->type == "$anyseq")
+ if (cell->type == ID($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) {
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index e0bb439f4..f910ea80d 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -88,25 +88,24 @@ struct BruteForceEquivChecker
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
- for (auto &w : mod1->wires_)
+ for (auto w : mod1->wires())
{
- RTLIL::Wire *wire1 = w.second;
- if (wire1->port_id == 0)
+ if (w->port_id == 0)
continue;
- if (mod2->wires_.count(wire1->name) == 0)
- log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
+ if (mod2->wire(w->name) == nullptr)
+ log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str());
- RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
- if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
- log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
+ RTLIL::Wire *w2 = mod2->wire(w->name);
+ if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output)
+ log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str());
- if (wire1->port_input) {
- mod1_inputs.append(wire1);
- mod2_inputs.append(wire2);
+ if (w->port_input) {
+ mod1_inputs.append(w);
+ mod2_inputs.append(w2);
} else {
- mod1_outputs.append(wire1);
- mod2_outputs.append(wire2);
+ mod1_outputs.append(w);
+ mod2_outputs.append(w2);
}
}
@@ -148,17 +147,17 @@ struct VlogHammerReporter
SatGen satgen(ez.get(), &sigmap);
satgen.model_undef = model_undef;
- for (auto &c : module->cells_)
- if (!satgen.importCell(c.second))
- log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
+ for (auto c : module->cells())
+ if (!satgen.importCell(c))
+ log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c->name), log_id(c->type));
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y)));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y)));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
@@ -253,7 +252,7 @@ struct VlogHammerReporter
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
- RTLIL::Wire *wire = module->wires_.at(inputs[i]);
+ RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
@@ -263,21 +262,21 @@ struct VlogHammerReporter
if (module == modules.front()) {
RTLIL::SigSpec sig(wire);
if (!ce.eval(sig))
- log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
+ log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
- log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
+ log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
}
}
- if (module->wires_.count("\\y") == 0)
- log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
+ if (module->wire(ID(y)) == nullptr)
+ log_error("No output wire (y) found in module %s!\n", log_id(module->name));
- RTLIL::SigSpec sig(module->wires_.at("\\y"));
+ RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
- // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
- log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
+ // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", log_id(module->name), log_signal(sig), log_signal(undef));
+ log_warning("Setting signal %s in module %s to undef.\n", log_signal(undef), log_id(module->name));
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
@@ -289,7 +288,7 @@ struct VlogHammerReporter
sat_check(module, recorded_set_vars, recorded_set_vals, sig, true);
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
- log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
+ log_error("Output (y) has a different width in module %s compared to rtl!\n", log_id(module->name));
for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
@@ -307,10 +306,10 @@ struct VlogHammerReporter
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
- if (design->modules_.count(esc_name) == 0)
+ if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
- modules.push_back(design->modules_.at(esc_name));
+ modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@@ -319,11 +318,11 @@ struct VlogHammerReporter
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
- if (mod->wires_.count(esc_name) == 0)
- log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
- RTLIL::Wire *port = mod->wires_.at(esc_name);
+ if (mod->wire(esc_name) == nullptr)
+ log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
+ RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
- log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
+ log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
width = port->width;
@@ -415,11 +414,11 @@ struct EvalPass : public Pass {
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules_.count(mod1_name) == 0)
+ if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
- if (design->modules_.count(mod2_name) == 0)
+ if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
- BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+ BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
@@ -441,13 +440,12 @@ struct EvalPass : public Pass {
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second)) {
- if (module)
- log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
- RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
- module = mod_it.second;
- }
+ for (auto mod : design->selected_modules()) {
+ if (module)
+ log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
+ log_id(module->name), log_id(mod->name));
+ module = mod;
+ }
if (module == NULL)
log_cmd_error("Can't perform EVAL on an empty selection!\n");
@@ -468,9 +466,9 @@ struct EvalPass : public Pass {
}
if (shows.size() == 0) {
- for (auto &it : module->wires_)
- if (it.second->port_output)
- shows.push_back(it.second->name.str());
+ for (auto w : module->wires())
+ if (w->port_output)
+ shows.push_back(w->name.str());
}
if (tables.empty())
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 29dfc7b19..80ab82cd5 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
- if (cell->type[0] == '\\' && !design->modules_.count(cell->type))
+ if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
return false;
return true;
}
@@ -85,27 +85,24 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
SigMap sigmap(module);
SigPool dffsignals;
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
- dffsignals.add(sigmap(it.second->getPort("\\Q")));
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type) && cell->hasPort(ID::Q))
+ dffsignals.add(sigmap(cell->getPort(ID::Q)));
}
- for (auto &it : module->wires_) {
- if (dffsignals.check_any(it.second))
- dff_wires.insert(it.first);
+ for (auto w : module->wires()) {
+ if (dffsignals.check_any(w))
+ dff_wires.insert(w->name);
}
}
-void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
- for (auto &it : module->cells_)
+ for (auto cell : module->selected_cells())
{
- if (!design->selected(module, it.second))
- continue;
-
dff_map_bit_info_t info;
info.bit_d = RTLIL::State::Sm;
info.bit_clk = RTLIL::State::Sm;
@@ -113,13 +110,13 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.clk_polarity = false;
info.arst_polarity = false;
info.arst_value = RTLIL::State::Sm;
- info.cell = it.second;
+ info.cell = cell;
- if (info.cell->type == "$dff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
- info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
- std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
+ if (info.cell->type == ID($dff)) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+ info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
bit_info[sig_q.at(i)] = info;
@@ -127,14 +124,14 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
continue;
}
- if (info.cell->type == "$adff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
- info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
- info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
- info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
- std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
- std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
+ if (info.cell->type == ID($adff)) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit();
+ info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
+ std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
+ std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
info.arst_value = arst_value.at(i);
@@ -143,33 +140,33 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
continue;
}
- if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
- info.clk_polarity = info.cell->type == "$_DFF_P_";
- info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
- bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+ if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+ info.clk_polarity = info.cell->type == ID($_DFF_P_);
+ info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+ bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
continue;
}
if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
- info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
+ info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit();
info.clk_polarity = info.cell->type[6] == 'P';
info.arst_polarity = info.cell->type[7] == 'P';
info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
- info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
- bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+ info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+ bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
continue;
}
}
std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
- if (!consider_wire(it.second, empty_dq_map))
+ if (!consider_wire(w, empty_dq_map))
continue;
- std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> bits_q = sigmap(w).to_sigbit_vector();
std::vector<RTLIL::SigBit> bits_d;
std::vector<RTLIL::State> arst_value;
std::set<RTLIL::Cell*> cells;
@@ -207,7 +204,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.arst_value = arst_value;
for (auto it : cells)
info.cells.push_back(it->name);
- map[it.first] = info;
+ map[w->name] = info;
}
}
@@ -314,26 +311,23 @@ struct ExposePass : public Pass {
RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires;
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
+ create_dff_dq_map(dff_dq_maps[mod], mod);
if (!flag_shared)
continue;
if (first_module == NULL) {
- for (auto &it : dff_dq_maps[mod_it.second])
+ for (auto &it : dff_dq_maps[mod])
shared_dff_wires.insert(it.first);
- first_module = mod_it.second;
+ first_module = mod;
} else {
std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) {
- if (!dff_dq_maps[mod_it.second].count(it))
+ if (!dff_dq_maps[mod].count(it))
continue;
- if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
+ if (!compare_wires(first_module->wire(it), mod->wire(it)))
continue;
new_shared_dff_wires.insert(it);
}
@@ -364,28 +358,23 @@ struct ExposePass : public Pass {
{
RTLIL::Module *first_module = NULL;
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff)
find_dff_wires(dff_wires, module);
if (first_module == NULL)
{
- for (auto &it : module->wires_)
- if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
- if (!flag_dff || dff_wires.count(it.first))
- shared_wires.insert(it.first);
+ for (auto w : module->wires())
+ if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module]))
+ if (!flag_dff || dff_wires.count(w->name))
+ shared_wires.insert(w->name);
if (flag_evert)
- for (auto &it : module->cells_)
- if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
- shared_cells.insert(it.first);
+ for (auto cell : module->cells())
+ if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell))
+ shared_cells.insert(cell->name);
first_module = module;
}
@@ -397,16 +386,16 @@ struct ExposePass : public Pass {
{
RTLIL::Wire *wire;
- if (module->wires_.count(it) == 0)
+ if (module->wire(it) == nullptr)
goto delete_shared_wire;
- wire = module->wires_.at(it);
+ wire = module->wire(it);
if (!design->selected(module, wire))
goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire;
- if (!compare_wires(first_module->wires_.at(it), wire))
+ if (!compare_wires(first_module->wire(it), wire))
goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire;
@@ -421,16 +410,16 @@ struct ExposePass : public Pass {
{
RTLIL::Cell *cell;
- if (module->cells_.count(it) == 0)
+ if (module->cell(it) == nullptr)
goto delete_shared_cell;
- cell = module->cells_.at(it);
+ cell = module->cell(it);
if (!design->selected(module, cell))
goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell;
- if (!compare_cells(first_module->cells_.at(it), cell))
+ if (!compare_cells(first_module->cell(it), cell))
goto delete_shared_cell;
if (0)
@@ -446,13 +435,8 @@ struct ExposePass : public Pass {
}
}
- for (auto &mod_it : design->modules_)
+ for (auto module : design->selected_modules())
{
- RTLIL::Module *module = mod_it.second;
-
- if (!design->selected(module))
- continue;
-
std::set<RTLIL::IdString> dff_wires;
if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module);
@@ -461,49 +445,49 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
- for (auto &it : module->wires_)
+ for (auto w : module->wires())
{
if (flag_shared) {
- if (shared_wires.count(it.first) == 0)
+ if (shared_wires.count(w->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module]))
+ if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module]))
continue;
- if (flag_dff && !dff_wires.count(it.first))
+ if (flag_dff && !dff_wires.count(w->name))
continue;
}
if (flag_input)
{
- if (!it.second->port_input) {
- it.second->port_input = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
- RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second));
- out_to_in_map.add(it.second, w);
+ if (!w->port_input) {
+ w->port_input = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+ RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
+ out_to_in_map.add(w, in_wire);
}
}
else
{
- if (!it.second->port_output) {
- it.second->port_output = true;
- log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
+ if (!w->port_output) {
+ w->port_output = true;
+ log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
+ RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
in_wire->port_input = true;
- out_to_in_map.add(sigmap(it.second), in_wire);
+ out_to_in_map.add(sigmap(w), in_wire);
}
}
}
if (flag_input)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_output(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_output(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -513,11 +497,11 @@ struct ExposePass : public Pass {
if (flag_cut)
{
- for (auto &it : module->cells_) {
- if (!ct.cell_known(it.second->type))
+ for (auto cell : module->cells()) {
+ if (!ct.cell_known(cell->type))
continue;
- for (auto &conn : it.second->connections_)
- if (ct.cell_input(it.second->type, conn.first))
+ for (auto &conn : cell->connections_)
+ if (ct.cell_input(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
}
@@ -529,10 +513,10 @@ struct ExposePass : public Pass {
for (auto &dq : dff_dq_maps[module])
{
- if (!module->wires_.count(dq.first))
+ if (module->wire(dq.first) == nullptr)
continue;
- RTLIL::Wire *wire = module->wires_.at(dq.first);
+ RTLIL::Wire *wire = module->wire(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
@@ -541,12 +525,12 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) {
- RTLIL::Cell *cell = module->cells_.at(cell_name);
- std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
+ RTLIL::Cell *cell = module->cell(cell_name);
+ std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
- cell->setPort("\\Q", cell_q_bits);
+ cell->setPort(ID::Q, cell_q_bits);
}
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
@@ -574,12 +558,12 @@ struct ExposePass : public Pass {
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
- RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
- c->parameters["\\A_SIGNED"] = 0;
- c->parameters["\\A_WIDTH"] = 1;
- c->parameters["\\Y_WIDTH"] = 1;
- c->setPort("\\A", info.sig_clk);
- c->setPort("\\Y", wire_c);
+ RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+ c->parameters[ID::A_SIGNED] = 0;
+ c->parameters[ID::A_WIDTH] = 1;
+ c->parameters[ID::Y_WIDTH] = 1;
+ c->setPort(ID::A, info.sig_clk);
+ c->setPort(ID::Y, wire_c);
}
if (info.sig_arst != RTLIL::State::Sm)
@@ -590,12 +574,12 @@ struct ExposePass : public Pass {
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
- RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
- c->parameters["\\A_SIGNED"] = 0;
- c->parameters["\\A_WIDTH"] = 1;
- c->parameters["\\Y_WIDTH"] = 1;
- c->setPort("\\A", info.sig_arst);
- c->setPort("\\Y", wire_r);
+ RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+ c->parameters[ID::A_SIGNED] = 0;
+ c->parameters[ID::A_WIDTH] = 1;
+ c->parameters[ID::Y_WIDTH] = 1;
+ c->setPort(ID::A, info.sig_arst);
+ c->setPort(ID::Y, wire_r);
}
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
@@ -609,25 +593,22 @@ struct ExposePass : public Pass {
{
std::vector<RTLIL::Cell*> delete_cells;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
if (flag_shared) {
- if (shared_cells.count(it.first) == 0)
+ if (shared_cells.count(cell->name) == 0)
continue;
} else {
- if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second))
+ if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell))
continue;
}
- RTLIL::Cell *cell = it.second;
-
- if (design->modules_.count(cell->type))
+ if (design->module(cell->type) != nullptr)
{
- RTLIL::Module *mod = design->modules_.at(cell->type);
+ RTLIL::Module *mod = design->module(cell->type);
- for (auto &it : mod->wires_)
+ for (auto p : mod->wires())
{
- RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output)
continue;
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index 00c098542..5066485aa 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -43,7 +43,7 @@ struct FmcombineWorker
FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
opts(opts), design(design), original(design->module(orig_type)),
- orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
+ orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str()))
{
}
@@ -106,7 +106,7 @@ struct FmcombineWorker
for (auto cell : original->cells()) {
if (design->module(cell->type) == nullptr) {
- if (opts.anyeq && cell->type.in("$anyseq", "$anyconst")) {
+ if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) {
Cell *gold = import_prim_cell(cell, "_gold");
for (auto &conn : cell->connections())
module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first));
@@ -114,10 +114,10 @@ struct FmcombineWorker
Cell *gold = import_prim_cell(cell, "_gold");
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
- if (cell->type.in("$ff", "$dff", "$dffe",
- "$dffsr", "$adff", "$dlatch", "$dlatchsr")) {
- SigSpec gold_q = gold->getPort("\\Q");
- SigSpec gate_q = gate->getPort("\\Q");
+ if (cell->type.in(ID($ff), ID($dff), ID($dffe),
+ ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) {
+ SigSpec gold_q = gold->getPort(ID::Q);
+ SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);
SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
module->addAssume(NEW_ID, eq, en);
@@ -359,7 +359,7 @@ struct FmcombinePass : public Pass {
Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
cell->attributes = gold_cell->attributes;
- cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src"));
+ cell->add_strpool_attribute(ID::src, gate_cell->get_strpool_attribute(ID::src));
log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc
index f3f00b382..555a28dc6 100644
--- a/passes/sat/fminit.cc
+++ b/passes/sat/fminit.cc
@@ -147,7 +147,7 @@ struct FminitPass : public Pass {
SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
Wire *outwire = module->addWire(NEW_ID);
- outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1;
+ outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1;
if (clksig.empty())
module->addFf(NEW_ID, insig, outwire);
@@ -161,7 +161,7 @@ struct FminitPass : public Pass {
if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
{
Wire *ffwire = module->addWire(NEW_ID);
- ffwire->attributes[ID(init)] = State::S0;
+ ffwire->attributes[ID::init] = State::S0;
SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);
if (clksig.empty())
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f29631639..5dfd7bd3f 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -614,29 +614,29 @@ struct FreduceWorker
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
- for (auto &it : module->wires_)
- if (it.second->port_input) {
- batches.push_back(sigmap(it.second).to_sigbit_set());
- bits_full_total += it.second->width;
+ for (auto w : module->wires())
+ if (w->port_input) {
+ batches.push_back(sigmap(w).to_sigbit_set());
+ bits_full_total += w->width;
}
- for (auto &it : module->cells_) {
- if (ct.cell_known(it.second->type)) {
+ for (auto cell : module->cells()) {
+ if (ct.cell_known(cell->type)) {
std::set<RTLIL::SigBit> inputs, outputs;
- for (auto &port : it.second->connections()) {
+ for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
- if (ct.cell_output(it.second->type, port.first))
+ if (ct.cell_output(cell->type, port.first))
outputs.insert(bits.begin(), bits.end());
else
inputs.insert(bits.begin(), bits.end());
}
- std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
+ std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
for (auto &bit : outputs)
drivers[bit] = drv;
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_NOT_")
- inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
+ if (inv_mode && cell->type == ID($_NOT_))
+ inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y))));
}
int bits_count = 0;
@@ -731,9 +731,9 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_ID);
- RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
- inv_cell->setPort("\\A", grp[0].bit);
- inv_cell->setPort("\\Y", inv_sig);
+ RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
+ inv_cell->setPort(ID::A, grp[0].bit);
+ inv_cell->setPort(ID::Y, inv_sig);
}
module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
@@ -828,10 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
- for (auto &mod_it : design->modules_) {
- RTLIL::Module *module = mod_it.second;
- if (design->selected(module))
- bitcount += FreduceWorker(design, module).run();
+ for (auto module : design->selected_modules()) {
+ bitcount += FreduceWorker(design, module).run();
}
log("Rewired a total of %d signal bits.\n", bitcount);
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 49ef40061..aeece9b94 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -66,50 +66,48 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
- if (design->modules_.count(gold_name) == 0)
+ if (design->module(gold_name) == nullptr)
log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
- if (design->modules_.count(gate_name) == 0)
+ if (design->module(gate_name) == nullptr)
log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
- if (design->modules_.count(miter_name) != 0)
+ if (design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
- RTLIL::Module *gold_module = design->modules_.at(gold_name);
- RTLIL::Module *gate_module = design->modules_.at(gate_name);
+ RTLIL::Module *gold_module = design->module(gold_name);
+ RTLIL::Module *gate_module = design->module(gate_name);
- for (auto &it : gold_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gold_wire : gold_module->wires()) {
+ if (gold_wire->port_id == 0)
continue;
- if (gate_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name);
+ if (gate_wire == nullptr)
goto match_gold_port_error;
- w2 = gate_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gold_wire->port_input != gate_wire->port_input)
goto match_gold_port_error;
- if (w1->port_output != w2->port_output)
+ if (gold_wire->port_output != gate_wire->port_output)
goto match_gold_port_error;
- if (w1->width != w2->width)
+ if (gold_wire->width != gate_wire->width)
goto match_gold_port_error;
continue;
match_gold_port_error:
- log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str());
}
- for (auto &it : gate_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gate_wire : gate_module->wires()) {
+ if (gate_wire->port_id == 0)
continue;
- if (gold_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name);
+ if (gold_wire == nullptr)
goto match_gate_port_error;
- w2 = gold_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gate_wire->port_input != gold_wire->port_input)
goto match_gate_port_error;
- if (w1->port_output != w2->port_output)
+ if (gate_wire->port_output != gold_wire->port_output)
goto match_gate_port_error;
- if (w1->width != w2->width)
+ if (gate_wire->width != gold_wire->width)
goto match_gate_port_error;
continue;
match_gate_port_error:
- log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
@@ -118,103 +116,101 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
miter_module->name = miter_name;
design->add(miter_module);
- RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
- RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
+ RTLIL::Cell *gold_cell = miter_module->addCell(ID(gold), gold_name);
+ RTLIL::Cell *gate_cell = miter_module->addCell(ID(gate), gate_name);
RTLIL::SigSpec all_conditions;
- for (auto &it : gold_module->wires_)
+ for (auto gold_wire : gold_module->wires())
{
- RTLIL::Wire *w1 = it.second;
-
- if (w1->port_input)
+ if (gold_wire->port_input)
{
- RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
- w2->port_input = true;
+ RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w->port_input = true;
- gold_cell->setPort(w1->name, w2);
- gate_cell->setPort(w1->name, w2);
+ gold_cell->setPort(gold_wire->name, w);
+ gate_cell->setPort(gold_wire->name, w);
}
- if (w1->port_output)
+ if (gold_wire->port_output)
{
- RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gold->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gold->port_output = flag_make_outputs;
- RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gate->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gate->port_output = flag_make_outputs;
- gold_cell->setPort(w1->name, w2_gold);
- gate_cell->setPort(w1->name, w2_gate);
+ gold_cell->setPort(gold_wire->name, w_gold);
+ gate_cell->setPort(gold_wire->name, w_gate);
RTLIL::SigSpec this_condition;
if (flag_ignore_gold_x)
{
- RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
- for (int i = 0; i < w2_gold->width; i++) {
- RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
- eqx_cell->parameters["\\A_WIDTH"] = 1;
- eqx_cell->parameters["\\B_WIDTH"] = 1;
- eqx_cell->parameters["\\Y_WIDTH"] = 1;
- eqx_cell->parameters["\\A_SIGNED"] = 0;
- eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
- eqx_cell->setPort("\\B", RTLIL::State::Sx);
- eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
+ RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
+ for (int i = 0; i < w_gold->width; i++) {
+ RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eqx_cell->parameters[ID::A_WIDTH] = 1;
+ eqx_cell->parameters[ID::B_WIDTH] = 1;
+ eqx_cell->parameters[ID::Y_WIDTH] = 1;
+ eqx_cell->parameters[ID::A_SIGNED] = 0;
+ eqx_cell->parameters[ID::B_SIGNED] = 0;
+ eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
+ eqx_cell->setPort(ID::B, RTLIL::State::Sx);
+ eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
}
- RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
- RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
-
- RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
- or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\A_SIGNED"] = 0;
- or_gold_cell->parameters["\\B_SIGNED"] = 0;
- or_gold_cell->setPort("\\A", w2_gold);
- or_gold_cell->setPort("\\B", gold_x);
- or_gold_cell->setPort("\\Y", gold_masked);
-
- RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
- or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\A_SIGNED"] = 0;
- or_gate_cell->parameters["\\B_SIGNED"] = 0;
- or_gate_cell->setPort("\\A", w2_gate);
- or_gate_cell->setPort("\\B", gold_x);
- or_gate_cell->setPort("\\Y", gate_masked);
-
- RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
- eq_cell->parameters["\\Y_WIDTH"] = 1;
- eq_cell->parameters["\\A_SIGNED"] = 0;
- eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", gold_masked);
- eq_cell->setPort("\\B", gate_masked);
- eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- this_condition = eq_cell->getPort("\\Y");
+ RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
+ RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
+
+ RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or));
+ or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::A_SIGNED] = 0;
+ or_gold_cell->parameters[ID::B_SIGNED] = 0;
+ or_gold_cell->setPort(ID::A, w_gold);
+ or_gold_cell->setPort(ID::B, gold_x);
+ or_gold_cell->setPort(ID::Y, gold_masked);
+
+ RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or));
+ or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::A_SIGNED] = 0;
+ or_gate_cell->parameters[ID::B_SIGNED] = 0;
+ or_gate_cell->setPort(ID::A, w_gate);
+ or_gate_cell->setPort(ID::B, gold_x);
+ or_gate_cell->setPort(ID::Y, gate_masked);
+
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ eq_cell->parameters[ID::Y_WIDTH] = 1;
+ eq_cell->parameters[ID::A_SIGNED] = 0;
+ eq_cell->parameters[ID::B_SIGNED] = 0;
+ eq_cell->setPort(ID::A, gold_masked);
+ eq_cell->setPort(ID::B, gate_masked);
+ eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ this_condition = eq_cell->getPort(ID::Y);
}
else
{
- RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
- eq_cell->parameters["\\Y_WIDTH"] = 1;
- eq_cell->parameters["\\A_SIGNED"] = 0;
- eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", w2_gold);
- eq_cell->setPort("\\B", w2_gate);
- eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- this_condition = eq_cell->getPort("\\Y");
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ eq_cell->parameters[ID::Y_WIDTH] = 1;
+ eq_cell->parameters[ID::A_SIGNED] = 0;
+ eq_cell->parameters[ID::B_SIGNED] = 0;
+ eq_cell->setPort(ID::A, w_gold);
+ eq_cell->setPort(ID::B, w_gate);
+ eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ this_condition = eq_cell->getPort(ID::Y);
}
if (flag_make_outcmp)
{
- RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name));
+ RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name));
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@@ -224,31 +220,31 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
if (all_conditions.size() != 1) {
- RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
- reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- reduce_cell->parameters["\\Y_WIDTH"] = 1;
- reduce_cell->parameters["\\A_SIGNED"] = 0;
- reduce_cell->setPort("\\A", all_conditions);
- reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
- all_conditions = reduce_cell->getPort("\\Y");
+ RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and));
+ reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ reduce_cell->parameters[ID::Y_WIDTH] = 1;
+ reduce_cell->parameters[ID::A_SIGNED] = 0;
+ reduce_cell->setPort(ID::A, all_conditions);
+ reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
+ all_conditions = reduce_cell->getPort(ID::Y);
}
if (flag_make_assert) {
- RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
- assert_cell->setPort("\\A", all_conditions);
- assert_cell->setPort("\\EN", State::S1);
+ RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert));
+ assert_cell->setPort(ID::A, all_conditions);
+ assert_cell->setPort(ID::EN, State::S1);
}
- RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
+ RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger));
w_trigger->port_output = true;
- RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
- not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
- not_cell->parameters["\\A_SIGNED"] = 0;
- not_cell->setPort("\\A", all_conditions);
- not_cell->setPort("\\Y", w_trigger);
+ RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not));
+ not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
+ not_cell->parameters[ID::A_SIGNED] = 0;
+ not_cell->setPort(ID::A, all_conditions);
+ not_cell->setPort(ID::Y, w_trigger);
miter_module->fixup_ports();
@@ -285,9 +281,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
IdString module_name = RTLIL::escape_id(args[argidx++]);
IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : "";
- if (design->modules_.count(module_name) == 0)
+ if (design->module(module_name) == nullptr)
log_cmd_error("Can't find module %s!\n", module_name.c_str());
- if (!miter_name.empty() && design->modules_.count(miter_name) != 0)
+ if (!miter_name.empty() && design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
Module *module = design->module(module_name);
@@ -302,7 +298,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
for (auto wire : module->wires())
wire->port_output = false;
- Wire *trigger = module->addWire("\\trigger");
+ Wire *trigger = module->addWire(ID(trigger));
trigger->port_output = true;
module->fixup_ports();
@@ -316,13 +312,13 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
vector<Cell*> cell_list = module->cells();
for (auto cell : cell_list)
{
- if (!cell->type.in("$assert", "$assume"))
+ if (!cell->type.in(ID($assert), ID($assume)))
continue;
- SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
- SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
+ SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
+ SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1);
- if (cell->type == "$assert") {
+ if (cell->type == ID($assert)) {
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
@@ -338,7 +334,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
else
{
Wire *assume_q = module->addWire(NEW_ID);
- assume_q->attributes["\\init"] = State::S0;
+ assume_q->attributes[ID::init] = State::S0;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index b53bbfeb2..af8ffca9e 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -439,7 +439,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
dict<SigBit, int> bit_user_cnt;
for (auto wire : module->wires()) {
- if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
+ if (wire->name[0] == '\\' && wire->attributes.count(ID::src))
sigmap.add(wire);
}
@@ -489,12 +489,12 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
entry.port = conn.first;
entry.portbit = i;
- for (auto &s : cell->get_strpool_attribute("\\src"))
+ for (auto &s : cell->get_strpool_attribute(ID::src))
entry.src.insert(s);
SigBit bit = sigmap(conn.second[i]);
if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
- for (auto &s : bit.wire->get_strpool_attribute("\\src"))
+ for (auto &s : bit.wire->get_strpool_attribute(ID::src))
entry.src.insert(s);
entry.wire = bit.wire->name;
entry.wirebit = bit.offset;
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 436ac1b01..6acdbc800 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -258,11 +258,11 @@ struct SatHelper
for (auto &it : module->wires_)
{
- if (it.second->attributes.count("\\init") == 0)
+ if (it.second->attributes.count(ID::init) == 0)
continue;
RTLIL::SigSpec lhs = sigmap(it.second);
- RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
+ RTLIL::SigSpec rhs = it.second->attributes.at(ID::init);
log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits;
@@ -518,9 +518,9 @@ struct SatHelper
} else {
for (auto &d : drivers)
for (auto &p : d->connections()) {
- if (d->type == "$dff" && p.first == "\\CLK")
+ if (d->type == ID($dff) && p.first == ID::CLK)
continue;
- if (d->type.begins_with("$_DFF_") && p.first == "\\C")
+ if (d->type.begins_with("$_DFF_") && p.first == ID::C)
continue;
queued_signals.add(handled_signals.remove(sigmap(p.second)));
}
@@ -675,9 +675,9 @@ struct SatHelper
strftime(stime, sizeof(stime), "%c", now);
std::string module_fname = "unknown";
- auto apos = module->attributes.find("\\src");
+ auto apos = module->attributes.find(ID::src);
if(apos != module->attributes.end())
- module_fname = module->attributes["\\src"].decode_string();
+ module_fname = module->attributes[ID::src].decode_string();
fprintf(f, "$date\n");
fprintf(f, " %s\n", stime);
@@ -1354,8 +1354,8 @@ struct SatPass : public Pass {
if (show_regs) {
pool<Wire*> reg_wires;
for (auto cell : module->cells()) {
- if (cell->type == "$dff" || cell->type.begins_with("$_DFF_"))
- for (auto bit : cell->getPort("\\Q"))
+ if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
+ for (auto bit : cell->getPort(ID::Q))
if (bit.wire)
reg_wires.insert(bit.wire);
}
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index d5634b26d..59bf5a712 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -108,8 +108,8 @@ struct SimInstance
}
}
- if (wire->attributes.count("\\init")) {
- Const initval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) {
state_nets[sig[i]] = initval[i];
@@ -132,24 +132,24 @@ struct SimInstance
upd_cells[bit].insert(cell);
}
- if (cell->type.in("$dff")) {
+ if (cell->type.in(ID($dff))) {
ff_state_t ff;
ff.past_clock = State::Sx;
- ff.past_d = Const(State::Sx, cell->getParam("\\WIDTH").as_int());
+ ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
ff_database[cell] = ff;
}
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
mem_state_t mem;
- mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort("\\WR_CLK")));
- mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort("\\WR_EN")));
- mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort("\\WR_ADDR")));
- mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort("\\WR_DATA")));
+ mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort(ID::WR_CLK)));
+ mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort(ID::WR_EN)));
+ mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort(ID::WR_ADDR)));
+ mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort(ID::WR_DATA)));
- mem.data = cell->getParam("\\INIT");
- int sz = cell->getParam("\\SIZE").as_int() * cell->getParam("\\WIDTH").as_int();
+ mem.data = cell->getParam(ID::INIT);
+ int sz = cell->getParam(ID::SIZE).as_int() * cell->getParam(ID::WIDTH).as_int();
if (GetSize(mem.data) > sz)
mem.data.bits.resize(sz);
@@ -160,7 +160,7 @@ struct SimInstance
mem_database[cell] = mem;
}
- if (cell->type.in("$assert", "$cover", "$assume")) {
+ if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
formal_database.insert(cell);
}
}
@@ -173,7 +173,7 @@ struct SimInstance
ff_state_t &ff = it.second;
zinit(ff.past_d);
- SigSpec qsig = cell->getPort("\\Q");
+ SigSpec qsig = cell->getPort(ID::Q);
Const qdata = get_state(qsig);
zinit(qdata);
set_state(qsig, qdata);
@@ -256,18 +256,18 @@ struct SimInstance
{
mem_state_t &mem = mem_database.at(cell);
- int num_rd_ports = cell->getParam("\\RD_PORTS").as_int();
+ int num_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
- int size = cell->getParam("\\SIZE").as_int();
- int offset = cell->getParam("\\OFFSET").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int size = cell->getParam(ID::SIZE).as_int();
+ int offset = cell->getParam(ID::OFFSET).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- if (cell->getParam("\\RD_CLK_ENABLE").as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).as_bool())
log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(cell));
- SigSpec rd_addr_sig = cell->getPort("\\RD_ADDR");
- SigSpec rd_data_sig = cell->getPort("\\RD_DATA");
+ SigSpec rd_addr_sig = cell->getPort(ID::RD_ADDR);
+ SigSpec rd_data_sig = cell->getPort(ID::RD_DATA);
for (int port_idx = 0; port_idx < num_rd_ports; port_idx++)
{
@@ -303,19 +303,19 @@ struct SimInstance
RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
bool has_a, has_b, has_c, has_d, has_s, has_y;
- has_a = cell->hasPort("\\A");
- has_b = cell->hasPort("\\B");
- has_c = cell->hasPort("\\C");
- has_d = cell->hasPort("\\D");
- has_s = cell->hasPort("\\S");
- has_y = cell->hasPort("\\Y");
+ has_a = cell->hasPort(ID::A);
+ has_b = cell->hasPort(ID::B);
+ has_c = cell->hasPort(ID::C);
+ has_d = cell->hasPort(ID::D);
+ has_s = cell->hasPort(ID::S);
+ has_y = cell->hasPort(ID::Y);
- if (has_a) sig_a = cell->getPort("\\A");
- if (has_b) sig_b = cell->getPort("\\B");
- if (has_c) sig_c = cell->getPort("\\C");
- if (has_d) sig_d = cell->getPort("\\D");
- if (has_s) sig_s = cell->getPort("\\S");
- if (has_y) sig_y = cell->getPort("\\Y");
+ if (has_a) sig_a = cell->getPort(ID::A);
+ if (has_b) sig_b = cell->getPort(ID::B);
+ if (has_c) sig_c = cell->getPort(ID::C);
+ if (has_d) sig_d = cell->getPort(ID::D);
+ if (has_s) sig_s = cell->getPort(ID::S);
+ if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
@@ -403,16 +403,16 @@ struct SimInstance
Cell *cell = it.first;
ff_state_t &ff = it.second;
- if (cell->type.in("$dff"))
+ if (cell->type.in(ID($dff)))
{
- bool clkpol = cell->getParam("\\CLK_POLARITY").as_bool();
- State current_clock = get_state(cell->getPort("\\CLK"))[0];
+ bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
+ State current_clock = get_state(cell->getPort(ID::CLK))[0];
if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
(ff.past_clock == State::S0 || current_clock != State::S0))
continue;
- if (set_state(cell->getPort("\\Q"), ff.past_d))
+ if (set_state(cell->getPort(ID::Q), ff.past_d))
did_something = true;
}
}
@@ -422,16 +422,16 @@ struct SimInstance
Cell *cell = it.first;
mem_state_t &mem = it.second;
- int num_wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int num_wr_ports = cell->getParam(ID::WR_PORTS).as_int();
- int size = cell->getParam("\\SIZE").as_int();
- int offset = cell->getParam("\\OFFSET").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int size = cell->getParam(ID::SIZE).as_int();
+ int offset = cell->getParam(ID::OFFSET).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- Const wr_clk_enable = cell->getParam("\\WR_CLK_ENABLE");
- Const wr_clk_polarity = cell->getParam("\\WR_CLK_POLARITY");
- Const current_wr_clk = get_state(cell->getPort("\\WR_CLK"));
+ Const wr_clk_enable = cell->getParam(ID::WR_CLK_ENABLE);
+ Const wr_clk_polarity = cell->getParam(ID::WR_CLK_POLARITY);
+ Const current_wr_clk = get_state(cell->getPort(ID::WR_CLK));
for (int port_idx = 0; port_idx < num_wr_ports; port_idx++)
{
@@ -439,9 +439,9 @@ struct SimInstance
if (wr_clk_enable[port_idx] == State::S0)
{
- addr = get_state(cell->getPort("\\WR_ADDR").extract(port_idx*abits, abits));
- data = get_state(cell->getPort("\\WR_DATA").extract(port_idx*width, width));
- enable = get_state(cell->getPort("\\WR_EN").extract(port_idx*width, width));
+ addr = get_state(cell->getPort(ID::WR_ADDR).extract(port_idx*abits, abits));
+ data = get_state(cell->getPort(ID::WR_DATA).extract(port_idx*width, width));
+ enable = get_state(cell->getPort(ID::WR_EN).extract(port_idx*width, width));
}
else
{
@@ -485,9 +485,9 @@ struct SimInstance
Cell *cell = it.first;
ff_state_t &ff = it.second;
- if (cell->type.in("$dff")) {
- ff.past_clock = get_state(cell->getPort("\\CLK"))[0];
- ff.past_d = get_state(cell->getPort("\\D"));
+ if (cell->type.in(ID($dff))) {
+ ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
+ ff.past_d = get_state(cell->getPort(ID::D));
}
}
@@ -496,28 +496,28 @@ struct SimInstance
Cell *cell = it.first;
mem_state_t &mem = it.second;
- mem.past_wr_clk = get_state(cell->getPort("\\WR_CLK"));
- mem.past_wr_en = get_state(cell->getPort("\\WR_EN"));
- mem.past_wr_addr = get_state(cell->getPort("\\WR_ADDR"));
- mem.past_wr_data = get_state(cell->getPort("\\WR_DATA"));
+ mem.past_wr_clk = get_state(cell->getPort(ID::WR_CLK));
+ mem.past_wr_en = get_state(cell->getPort(ID::WR_EN));
+ mem.past_wr_addr = get_state(cell->getPort(ID::WR_ADDR));
+ mem.past_wr_data = get_state(cell->getPort(ID::WR_DATA));
}
for (auto cell : formal_database)
{
string label = log_id(cell);
- if (cell->attributes.count("\\src"))
- label = cell->attributes.at("\\src").decode_string();
+ if (cell->attributes.count(ID::src))
+ label = cell->attributes.at(ID::src).decode_string();
- State a = get_state(cell->getPort("\\A"))[0];
- State en = get_state(cell->getPort("\\EN"))[0];
+ State a = get_state(cell->getPort(ID::A))[0];
+ State en = get_state(cell->getPort(ID::EN))[0];
- if (cell->type == "$cover" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($cover) && en == State::S1 && a != State::S1)
log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
- if (cell->type == "$assume" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
- if (cell->type == "$assert" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
}
@@ -533,22 +533,22 @@ struct SimInstance
wbmods.insert(module);
for (auto wire : module->wires())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
for (auto &it : ff_database)
{
Cell *cell = it.first;
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_q = cell->getPort(ID::Q);
Const initval = get_state(sig_q);
for (int i = 0; i < GetSize(sig_q); i++)
{
Wire *w = sig_q[i].wire;
- if (w->attributes.count("\\init") == 0)
- w->attributes["\\init"] = Const(State::Sx, GetSize(w));
+ if (w->attributes.count(ID::init) == 0)
+ w->attributes[ID::init] = Const(State::Sx, GetSize(w));
- w->attributes["\\init"][sig_q[i].offset] = initval[i];
+ w->attributes[ID::init][sig_q[i].offset] = initval[i];
}
}
@@ -564,7 +564,7 @@ struct SimInstance
initval.bits.pop_back();
}
- cell->setParam("\\INIT", initval);
+ cell->setParam(ID::INIT, initval);
}
for (auto it : children)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 02:39:52 +0000