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-rw-r--r--passes/techmap/abc.cc93
1 files changed, 66 insertions, 27 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index c0cfe2f36..9f963a8bf 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff)
{
- if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
if (clk_polarity != (cell->type == "$_DFF_P_"))
return;
@@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
goto matching_dff;
}
- if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+ if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
- if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
+ if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
return;
- if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
+ if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
@@ -333,17 +333,17 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
{
std::string abc_sname = abc_name.substr(1);
bool isnew = false;
- if (abc_sname.substr(0, 4) == "new_")
+ if (abc_sname.compare(0, 4, "new_") == 0)
{
abc_sname.erase(0, 4);
isnew = true;
}
- if (abc_sname.substr(0, 5) == "ys__n")
+ if (abc_sname.compare(0, 5, "ys__n") == 0)
{
abc_sname.erase(0, 5);
if (std::isdigit(abc_sname.at(0)))
{
- int sid = std::stoi(abc_sname);
+ int sid = std::atoi(abc_sname.c_str());
size_t postfix_start = abc_sname.find_first_not_of("0123456789");
std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
@@ -941,33 +941,33 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_BUF_"));
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOT_"));
- if (enabled_gates.empty() || enabled_gates.count("AND"))
+ if (enabled_gates.count("AND"))
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_AND_"));
- if (enabled_gates.empty() || enabled_gates.count("NAND"))
+ if (enabled_gates.count("NAND"))
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NAND_"));
- if (enabled_gates.empty() || enabled_gates.count("OR"))
+ if (enabled_gates.count("OR"))
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at("$_OR_"));
- if (enabled_gates.empty() || enabled_gates.count("NOR"))
+ if (enabled_gates.count("NOR"))
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_NOR_"));
- if (enabled_gates.empty() || enabled_gates.count("XOR"))
+ if (enabled_gates.count("XOR"))
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XOR_"));
- if (enabled_gates.empty() || enabled_gates.count("XNOR"))
+ if (enabled_gates.count("XNOR"))
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_XNOR_"));
- if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
+ if (enabled_gates.count("ANDNOT"))
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ANDNOT_"));
- if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
+ if (enabled_gates.count("ORNOT"))
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_ORNOT_"));
- if (enabled_gates.empty() || enabled_gates.count("AOI3"))
+ if (enabled_gates.count("AOI3"))
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI3_"));
- if (enabled_gates.empty() || enabled_gates.count("OAI3"))
+ if (enabled_gates.count("OAI3"))
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI3_"));
- if (enabled_gates.empty() || enabled_gates.count("AOI4"))
+ if (enabled_gates.count("AOI4"))
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_AOI4_"));
- if (enabled_gates.empty() || enabled_gates.count("OAI4"))
+ if (enabled_gates.count("OAI4"))
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at("$_OAI4_"));
- if (enabled_gates.empty() || enabled_gates.count("MUX"))
+ if (enabled_gates.count("MUX"))
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_MUX_"));
- if (enabled_gates.empty() || enabled_gates.count("NMUX"))
+ if (enabled_gates.count("NMUX"))
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at("$_NMUX_"));
if (map_mux4)
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at("$_MUX_"));
@@ -1411,7 +1411,9 @@ struct AbcPass : public Pass {
// log("\n");
log(" -g type1,type2,...\n");
log(" Map to the specified list of gate types. Supported gates types are:\n");
- log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,\n");
+ log(" NMUX, AOI3, OAI3, AOI4, OAI4.\n");
log(" (The NOT gate is always added to this list automatically.)\n");
log("\n");
log(" The following aliases can be used to reference common sets of gate types:\n");
@@ -1423,9 +1425,13 @@ struct AbcPass : public Pass {
log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
log("\n");
+ log(" The alias 'all' represent the full set of all gate types.\n");
+ log("\n");
log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
log("\n");
+ log(" The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.\n");
+ log("\n");
log(" -dff\n");
log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
log(" clock domains are automatically partitioned in clock domains and each\n");
@@ -1584,7 +1590,7 @@ struct AbcPass : public Pass {
else if (GetSize(parts) == 1)
lut_costs.push_back(atoi(parts.at(0).c_str()));
else if (GetSize(parts) == 2)
- while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
+ while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str()))
lut_costs.push_back(atoi(parts.at(1).c_str()));
else
log_cmd_error("Invalid -luts syntax.\n");
@@ -1701,6 +1707,22 @@ struct AbcPass : public Pass {
gate_list.push_back("ORNOT");
goto ok_alias;
}
+ if (g == "all") {
+ gate_list.push_back("AND");
+ gate_list.push_back("NAND");
+ gate_list.push_back("OR");
+ gate_list.push_back("NOR");
+ gate_list.push_back("XOR");
+ gate_list.push_back("XNOR");
+ gate_list.push_back("ANDNOT");
+ gate_list.push_back("ORNOT");
+ gate_list.push_back("AOI3");
+ gate_list.push_back("OAI3");
+ gate_list.push_back("AOI4");
+ gate_list.push_back("OAI4");
+ gate_list.push_back("MUX");
+ gate_list.push_back("NMUX");
+ }
cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
ok_gate:
gate_list.push_back(g);
@@ -1752,6 +1774,23 @@ struct AbcPass : public Pass {
if (!constr_file.empty() && liberty_file.empty())
log_cmd_error("Got -constr but no -liberty!\n");
+ if (enabled_gates.empty()) {
+ enabled_gates.insert("AND");
+ enabled_gates.insert("NAND");
+ enabled_gates.insert("OR");
+ enabled_gates.insert("NOR");
+ enabled_gates.insert("XOR");
+ enabled_gates.insert("XNOR");
+ enabled_gates.insert("ANDNOT");
+ enabled_gates.insert("ORNOT");
+ // enabled_gates.insert("AOI3");
+ // enabled_gates.insert("OAI3");
+ // enabled_gates.insert("AOI4");
+ // enabled_gates.insert("OAI4");
+ enabled_gates.insert("MUX");
+ // enabled_gates.insert("NMUX");
+ }
+
for (auto mod : design->selected_modules())
{
if (mod->processes.size() > 0) {
@@ -1822,15 +1861,15 @@ struct AbcPass : public Pass {
}
}
- if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
+ if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
- if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
+ if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
{
- bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
- bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
+ bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
+ bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 01:57:25 +0000