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-rw-r--r--passes/techmap/abc9_ops.cc183
1 files changed, 100 insertions, 83 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 98d0207c4..29fe74ec7 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
@@ -155,21 +155,6 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
r.first->second = new Design;
Design *unmap_design = r.first->second;
- static const pool<IdString> seq_types{
- ID($dff), ID($dffsr), ID($adff),
- ID($dlatch), ID($dlatchsr), ID($sr),
- ID($mem),
- ID($_DFF_N_), ID($_DFF_P_),
- ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
- ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
- ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
- ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
- ID($_DLATCH_N_), ID($_DLATCH_P_),
- ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
- ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
- ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
- };
-
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);
@@ -189,16 +174,22 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
derived_type = inst_module->derive(design, cell->parameters);
derived_module = design->module(derived_type);
}
- if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
- continue;
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
if (!dff_mode)
continue;
}
else {
- if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass))
+ if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass)) {
+ if (unmap_design->module(derived_type)) {
+ // If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if
+ // it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties
+ // as a compatible type, yet will be safely unmapped later
+ cell->type = derived_type;
+ cell->parameters.clear();
+ }
continue;
+ }
}
if (!unmap_design->module(derived_type)) {
@@ -223,7 +214,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
}
else if (derived_module->get_bool_attribute(ID::abc9_box)) {
for (auto derived_cell : derived_module->cells())
- if (seq_types.count(derived_cell->type)) {
+ if (derived_cell->is_mem_cell() || RTLIL::builtin_ff_cell_types().count(derived_cell->type)) {
derived_module->set_bool_attribute(ID::abc9_box, false);
derived_module->set_bool_attribute(ID::abc9_bypass);
break;
@@ -441,6 +432,8 @@ void prep_bypass(RTLIL::Design *design)
}
}
unmap_module->fixup_ports();
+
+ design->scratchpad_set_bool("abc9_ops.prep_bypass.did_something", true);
}
}
@@ -459,7 +452,14 @@ void prep_dff(RTLIL::Design *design)
if (!inst_module->get_bool_attribute(ID::abc9_flop))
continue;
log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
- log_assert(cell->parameters.empty());
+ if (!cell->parameters.empty())
+ {
+ // At this stage of the ABC9 flow, cells instantiating (* abc9_flop *) modules must not contain any parameters -- instead it should
+ // be instantiating the derived module which will have had any parameters constant-propagated.
+ // This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
+ // Please file a bug report!
+ log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", log_id(cell->name), log_id(cell->type));
+ }
modules_sel.select(inst_module);
}
}
@@ -544,18 +544,31 @@ void prep_dff_unmap(RTLIL::Design *design)
}
}
-void mark_scc(RTLIL::Module *module)
+void break_scc(RTLIL::Module *module)
{
// For every unique SCC found, (arbitrarily) find the first
- // cell in the component, and replace its output connections
- // with a new wire driven by the old connection but with a
- // special (* abc9_keep *) attribute set (which is used by
- // write_xaiger to break this wire into PI and POs)
+ // cell in the component, and interrupt all its output connections
+ // with the $__ABC9_SCC_BREAKER cell
+
+ // Do not break SCCs which have a cell instantiating an abc9_bypass-able
+ // module (but which wouldn't have been bypassed)
+ auto design = module->design;
+ pool<RTLIL::Cell*> scc_cells;
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID::abc9_scc_id);
if (it == cell->attributes.end())
continue;
+ scc_cells.insert(cell);
+ auto inst_module = design->module(cell->type);
+ if (inst_module && inst_module->has_attribute(ID::abc9_bypass))
+ ids_seen.insert(it->second);
+ }
+
+ SigSpec I, O;
+ for (auto cell : scc_cells) {
+ auto it = cell->attributes.find(ID::abc9_scc_id);
+ log_assert(it != cell->attributes.end());
auto id = it->second;
auto r = ids_seen.insert(id);
cell->attributes.erase(it);
@@ -565,12 +578,21 @@ void mark_scc(RTLIL::Module *module)
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
- w->set_bool_attribute(ID::abc9_keep);
- module->connect(w, c.second);
+ I.append(w);
+ O.append(c.second);
c.second = w;
}
}
}
+
+ if (!I.empty())
+ {
+ auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
+ log_assert(GetSize(I) == GetSize(O));
+ cell->setParam(ID::WIDTH, GetSize(I));
+ cell->setPort(ID::I, std::move(I));
+ cell->setPort(ID::O, std::move(O));
+ }
}
void prep_delays(RTLIL::Design *design, bool dff_mode)
@@ -626,40 +648,38 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto inst_module = design->module(cell->type);
log_assert(inst_module);
- auto &t = timing.at(cell->type).required;
- for (auto &conn : cell->connections_) {
- auto port_wire = inst_module->wire(conn.first);
+ for (auto &i : timing.at(cell->type).required) {
+ auto port_wire = inst_module->wire(i.first.name);
if (!port_wire)
log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
- log_id(conn.first), log_id(cell), log_id(cell->type), log_id(module));
- if (!port_wire->port_input)
- continue;
- if (conn.second.is_fully_const())
+ log_id(i.first.name), log_id(cell), log_id(cell->type), log_id(module));
+ log_assert(port_wire->port_input);
+
+ auto d = i.second.first;
+ if (d == 0)
continue;
- SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
- for (int i = 0; i < GetSize(conn.second); i++) {
- auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
- if (d == 0)
- continue;
+ auto offset = i.first.offset;
+ auto O = module->addWire(NEW_ID);
+ auto rhs = cell->getPort(i.first.name);
#ifndef NDEBUG
- if (ys_debug(1)) {
- static std::set<std::tuple<IdString,IdString,int>> seen;
- if (seen.emplace(cell->type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
- log_id(cell->type), log_id(conn.first), i, d);
- }
+ if (ys_debug(1)) {
+ static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
+ if (seen.emplace(cell->type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
+ log_id(cell->type), log_id(i.first.name), offset, d);
+ }
#endif
- auto r = box_cache.insert(d);
- if (r.second) {
- r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
- log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
- }
- auto box = module->addCell(NEW_ID, r.first->second);
- box->setPort(ID::I, conn.second[i]);
- box->setPort(ID::O, O[i]);
- conn.second[i] = O[i];
+ auto r = box_cache.insert(d);
+ if (r.second) {
+ r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
+ log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
+ auto box = module->addCell(NEW_ID, r.first->second);
+ box->setPort(ID::I, rhs[offset]);
+ box->setPort(ID::O, O);
+ rhs[offset] = O;
+ cell->setPort(i.first.name, rhs);
}
}
}
@@ -721,10 +741,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
bit_users[bit].insert(cell->name);
if (cell->output(conn.first) && !abc9_flop)
- for (const auto &chunk : conn.second.chunks())
- if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
- for (auto b : sigmap(SigSpec(chunk)))
- bit_drivers[b].insert(cell->name);
+ for (auto bit : sigmap(conn.second))
+ bit_drivers[bit].insert(cell->name);
}
toposort.node(cell->name);
}
@@ -778,7 +796,14 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
continue;
if (!box_module->get_bool_attribute(ID::abc9_box))
continue;
- log_assert(cell->parameters.empty());
+ if (!cell->parameters.empty())
+ {
+ // At this stage of the ABC9 flow, cells instantiating (* abc9_box *) modules must not contain any parameters -- instead it should
+ // be instantiating the derived module which will have had any parameters constant-propagated.
+ // This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design.
+ // Please file a bug report!
+ log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", log_id(cell_name), log_id(cell->type));
+ }
log_assert(box_module->get_blackbox_attribute());
cell->attributes[ID::abc9_box_seq] = box_count++;
@@ -787,7 +812,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
- holes_cell = holes_module->addCell(cell->name, cell->type);
+ holes_cell = holes_module->addCell(NEW_ID, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
@@ -917,15 +942,8 @@ void prep_box(RTLIL::Design *design)
{
TimingInfo timing;
- std::stringstream ss;
int abc9_box_id = 1;
- for (auto module : design->modules()) {
- auto it = module->attributes.find(ID::abc9_box_id);
- if (it == module->attributes.end())
- continue;
- abc9_box_id = std::max(abc9_box_id, it->second.as_int());
- }
-
+ std::stringstream ss;
dict<IdString,std::vector<IdString>> box_ports;
for (auto module : design->modules()) {
auto it = module->attributes.find(ID::abc9_box);
@@ -986,16 +1004,16 @@ void prep_box(RTLIL::Design *design)
log_assert(GetSize(wire) == 1);
auto it = t.find(TimingInfo::NameBit(port_name,0));
if (it == t.end())
- // Assume no connectivity if no setup time
- ss << "-";
+ // Assume that no setup time means zero
+ ss << 0;
else {
- ss << it->second;
+ ss << it->second.first;
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
- log_id(port_name), it->second);
+ log_id(port_name), it->second.first);
}
#endif
}
@@ -1416,7 +1434,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
- wire->attributes.erase(ID::abc9_keep);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
@@ -1579,11 +1596,11 @@ struct Abc9OpsPass : public Pass {
log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
log(" certain required times.\n");
log("\n");
- log(" -mark_scc\n");
+ log(" -break_scc\n");
log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
- log(" (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
- log(" wires driven by this cell's outputs with a (* keep *) attribute in order\n");
- log(" to break the SCC. this temporary attribute will be removed on -reintegrate.\n");
+ log(" (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt all wires\n");
+ log(" driven by this cell's outputs with a temporary $__ABC9_SCC_BREAKER cell\n");
+ log(" to break the SCC.\n");
log("\n");
log(" -prep_xaiger\n");
log(" prepare the design for XAIGER output. this includes computing the\n");
@@ -1620,7 +1637,7 @@ struct Abc9OpsPass : public Pass {
bool check_mode = false;
bool prep_delays_mode = false;
- bool mark_scc_mode = false;
+ bool break_scc_mode = false;
bool prep_hier_mode = false;
bool prep_bypass_mode = false;
bool prep_dff_mode = false, prep_dff_submod_mode = false, prep_dff_unmap_mode = false;
@@ -1642,8 +1659,8 @@ struct Abc9OpsPass : public Pass {
valid = true;
continue;
}
- if (arg == "-mark_scc") {
- mark_scc_mode = true;
+ if (arg == "-break_scc") {
+ break_scc_mode = true;
valid = true;
continue;
}
@@ -1719,7 +1736,7 @@ struct Abc9OpsPass : public Pass {
extra_args(args, argidx, design);
if (!valid)
- log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
+ log_cmd_error("At least one of -check, -break_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
if (dff_mode && !check_mode && !prep_hier_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode)
log_cmd_error("'-dff' option is only relevant for -prep_{hier,delay,xaiger} or -reintegrate.\n");
@@ -1756,8 +1773,8 @@ struct Abc9OpsPass : public Pass {
write_lut(mod, write_lut_dst);
if (!write_box_dst.empty())
write_box(mod, write_box_dst);
- if (mark_scc_mode)
- mark_scc(mod);
+ if (break_scc_mode)
+ break_scc(mod);
if (prep_xaiger_mode)
prep_xaiger(mod, dff_mode);
if (reintegrate_mode)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 21:26:53 +0000