1 files changed, 290 insertions, 70 deletions

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cc22fd474..7f3bbc7ad 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -23,6 +23,8 @@
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
 
+#define ABC9_DELAY_BASE_ID 9000
+
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
@@ -33,6 +35,62 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
 	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 }
 
+void check(RTLIL::Design *design)
+{
+	dict<IdString,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		auto flop = m->get_bool_attribute(ID(abc9_flop));
+		auto it = m->attributes.find(ID(abc9_box_id));
+		if (it == m->attributes.end()) {
+			if (flop)
+				log_error("Module '%s' contains (* abc9_flop *) but not (* abc9_box_id=<int> *).\n", log_id(m));
+			continue;
+		}
+		if (m->name.begins_with("$paramod"))
+			continue;
+		auto id = it->second.as_int();
+		auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+		if (!r.second)
+			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+					log_id(m), id, log_id(r.first->second));
+
+		// Make carry in the last PI, and carry out the last PO
+		//   since ABC requires it this way
+		IdString carry_in, carry_out;
+		for (const auto &port_name : m->ports) {
+			auto w = m->wire(port_name);
+			log_assert(w);
+			if (w->get_bool_attribute("\\abc9_carry")) {
+				if (w->port_input) {
+					if (carry_in != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
+					carry_in = port_name;
+				}
+				if (w->port_output) {
+					if (carry_out != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
+					carry_out = port_name;
+				}
+			}
+		}
+
+		if (carry_in != IdString() && carry_out == IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
+		if (carry_in == IdString() && carry_out != IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
+
+		if (flop) {
+			int num_outputs = 0;
+			for (auto port_name : m->ports) {
+				auto wire = m->wire(port_name);
+				if (wire->port_output) num_outputs++;
+			}
+			if (num_outputs != 1)
+				log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+		}
+	}
+}
+
 void break_scc(RTLIL::Module *module)
 {
 	// For every unique SCC found, (arbitrarily) find the first
@@ -302,6 +360,7 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		}
 
 		cell->attributes["\\abc9_box_seq"] = box_list.size();
+		//log_debug("%s.%s is box %d\n", log_id(module), log_id(cell), box_list.size());
 		box_list.emplace_back(cell);
 	}
 	log_assert(!box_list.empty());
@@ -319,13 +378,12 @@ void prep_holes(RTLIL::Module *module, bool dff)
 		log_assert(orig_box_module);
 		IdString derived_name = orig_box_module->derive(design, cell->parameters);
 		RTLIL::Module* box_module = design->module(derived_name);
+		//cell->type = derived_name;
+		//cell->parameters.clear();
 
 		auto r = cell_cache.insert(derived_name);
 		auto &holes_cell = r.first->second;
 		if (r.second) {
-			if (box_module->has_processes())
-				Pass::call_on_module(design, box_module, "proc");
-
 			auto r2 = box_ports.insert(cell->type);
 			if (r2.second) {
 				// Make carry in the last PI, and carry out the last PO
@@ -335,25 +393,15 @@ void prep_holes(RTLIL::Module *module, bool dff)
 					auto w = box_module->wire(port_name);
 					log_assert(w);
 					if (w->get_bool_attribute("\\abc9_carry")) {
-						if (w->port_input) {
-							if (carry_in != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
+						if (w->port_input)
 							carry_in = port_name;
-						}
-						if (w->port_output) {
-							if (carry_out != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
+						if (w->port_output)
 							carry_out = port_name;
-						}
 					}
 					else
 						r2.first->second.push_back(port_name);
 				}
 
-				if (carry_in != IdString() && carry_out == IdString())
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
-				if (carry_in == IdString() && carry_out != IdString())
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
 				if (carry_in != IdString()) {
 					r2.first->second.push_back(carry_in);
 					r2.first->second.push_back(carry_out);
@@ -363,6 +411,9 @@ void prep_holes(RTLIL::Module *module, bool dff)
 			if (box_module->get_bool_attribute("\\whitebox")) {
 				holes_cell = holes_module->addCell(cell->name, derived_name);
 
+				if (box_module->has_processes())
+					Pass::call_on_module(design, box_module, "proc");
+
 				int box_inputs = 0;
 				for (auto port_name : box_ports.at(cell->type)) {
 					RTLIL::Wire *w = box_module->wire(port_name);
@@ -422,6 +473,159 @@ void prep_holes(RTLIL::Module *module, bool dff)
 	}
 }
 
+void prep_times(RTLIL::Design *design)
+{
+	std::set<int> delays;
+	pool<Module*> flops;
+	std::vector<Cell*> boxes;
+	std::map<int,std::vector<int>> requireds;
+	for (auto module : design->selected_modules()) {
+		if (module->processes.size() > 0) {
+			log("Skipping module %s as it contains processes.\n", log_id(module));
+			continue;
+		}
+
+		boxes.clear();
+		for (auto cell : module->cells()) {
+			if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+				continue;
+
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			if (!inst_module)
+				continue;
+			if (!inst_module->get_blackbox_attribute())
+				continue;
+			if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+				flops.insert(inst_module);
+				continue;
+			}
+			// All remaining boxes are combinatorial and cannot
+			//   contain a required time
+			if (inst_module->attributes.count(ID(abc9_box_id)))
+				continue;
+			boxes.emplace_back(cell);
+		}
+
+		delays.clear();
+		requireds.clear();
+		for (auto cell : boxes) {
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			log_assert(inst_module);
+			for (auto &conn : cell->connections_) {
+				auto port_wire = inst_module->wire(conn.first);
+				if (!port_wire->port_input)
+					continue;
+
+				auto it = port_wire->attributes.find("\\abc9_required");
+				if (it == port_wire->attributes.end())
+					continue;
+
+				int count = 0;
+				requireds.clear();
+				if (it->second.flags == 0) {
+					count = 1;
+					requireds[it->second.as_int()].push_back(0);
+				}
+				else
+					for (const auto &tok : split_tokens(it->second.decode_string()))
+						requireds[atoi(tok.c_str())].push_back(count++);
+				if (count > 1 && count != GetSize(port_wire))
+					log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
+							GetSize(port_wire), log_signal(it->second), count);
+
+				SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+				for (const auto &i : requireds) {
+#ifndef NDEBUG
+					if (ys_debug(1)) {
+						static std::set<std::pair<IdString,IdString>> seen;
+						if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first);
+					}
+#endif
+					delays.insert(i.first);
+					for (auto offset : i.second) {
+						auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+						box->setPort(ID(I), conn.second[offset]);
+						box->setPort(ID(O), O[offset]);
+						box->setParam(ID(DELAY), i.first);
+						conn.second[offset] = O[offset];
+					}
+				}
+			}
+		}
+
+		std::stringstream ss;
+		bool first = true;
+		for (auto d : delays) {
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			ss << d;
+		}
+		module->attributes[ID(abc9_delays)] = ss.str();
+	}
+
+	std::stringstream ss;
+	for (auto flop_module : flops) {
+		// Skip parameterised flop_modules for now (since we do not
+		//   dynamically generate the abc9_box_id)
+		if (flop_module->name.begins_with("$paramod"))
+			continue;
+
+		int num_inputs = 0, num_outputs = 0;
+		for (auto port_name : flop_module->ports) {
+			auto wire = flop_module->wire(port_name);
+			if (wire->port_input) num_inputs++;
+			if (wire->port_output) num_outputs++;
+		}
+		log_assert(num_outputs == 1);
+
+		ss << log_id(flop_module) << " " << flop_module->attributes.at(ID(abc9_box_id)).as_int();
+		ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
+		bool first = true;
+		for (auto port_name : flop_module->ports) {
+			auto wire = flop_module->wire(port_name);
+			if (!wire->port_input)
+				continue;
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			ss << wire->attributes.at("\\abc9_required", 0).as_int();
+		}
+		// Last input is 'abc9_ff.Q'
+		ss << " 0" << std::endl << std::endl;
+	}
+	design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
+}
+
+void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+
+	// Since ABC can only accept one box file, we have to copy
+	//   over the existing box file
+	if (src != "(null)") {
+		std::ifstream ifs(src);
+		ofs << ifs.rdbuf() << std::endl;
+		ifs.close();
+	}
+
+	ofs << module->design->scratchpad_get_string("abc9_ops.box.flops");
+
+	auto it = module->attributes.find(ID(abc9_delays));
+	if (it != module->attributes.end()) {
+		for (const auto &tok : split_tokens(it->second.decode_string())) {
+			int d = atoi(tok.c_str());
+			ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
+			ofs << d << std::endl;
+		}
+		module->attributes.erase(it);
+	}
+
+	ofs.close();
+}
+
 void reintegrate(RTLIL::Module *module)
 {
 	auto design = module->design;
@@ -437,8 +641,6 @@ void reintegrate(RTLIL::Module *module)
 		module->addWire(remap_name(w->name), GetSize(w));
 
 	dict<IdString,IdString> box_lookup;
-	dict<IdString,std::vector<IdString>> box_ports;
-
 	for (auto m : design->modules()) {
 		auto it = m->attributes.find(ID(abc9_box_id));
 		if (it == m->attributes.end())
@@ -446,51 +648,19 @@ void reintegrate(RTLIL::Module *module)
 		if (m->name.begins_with("$paramod"))
 			continue;
 		auto id = it->second.as_int();
-		auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
-		if (!r.second)
-			log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-					log_id(m), id, log_id(r.first->second));
+		auto r YS_ATTRIBUTE(unused) = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
 		log_assert(r.second);
-
-		auto r2 = box_ports.insert(m->name);
-		if (r2.second) {
-			// Make carry in the last PI, and carry out the last PO
-			//   since ABC requires it this way
-			IdString carry_in, carry_out;
-			for (const auto &port_name : m->ports) {
-				auto w = m->wire(port_name);
-				log_assert(w);
-				if (w->get_bool_attribute("\\abc9_carry")) {
-					if (w->port_input) {
-						if (carry_in != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_in = port_name;
-					}
-					if (w->port_output) {
-						if (carry_out != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
-						carry_out = port_name;
-					}
-				}
-				else
-					r2.first->second.push_back(port_name);
-			}
-
-			if (carry_in != IdString() && carry_out == IdString())
-				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-			if (carry_in == IdString() && carry_out != IdString())
-				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-			if (carry_in != IdString()) {
-				r2.first->second.push_back(carry_in);
-				r2.first->second.push_back(carry_out);
-			}
-		}
 	}
 
+	pool<IdString> delay_boxes;
 	std::vector<Cell*> boxes;
 	for (auto cell : module->cells().to_vector()) {
 		if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
 			module->remove(cell);
+		else if (cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
+			delay_boxes.insert(cell->name);
+			module->remove(cell);
+		}
 		else if (cell->attributes.erase("\\abc9_box_seq"))
 			boxes.emplace_back(cell);
 	}
@@ -500,6 +670,7 @@ void reintegrate(RTLIL::Module *module)
 	dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
 	dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
 
+	dict<IdString,std::vector<IdString>> box_ports;
 	std::map<IdString, int> cell_stats;
 	for (auto mapped_cell : mapped_mod->cells())
 	{
@@ -550,16 +721,6 @@ void reintegrate(RTLIL::Module *module)
 		}
 
 		if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
-			// Convert buffer into direct connection
-			if (mapped_cell->type == ID($lut) &&
-					GetSize(mapped_cell->getPort(ID::A)) == 1 &&
-					mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
-				SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
-				SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
-				module->connect(my_y, my_a);
-				log_abort();
-				continue;
-			}
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
 			cell->attributes = mapped_cell->attributes;
@@ -587,6 +748,16 @@ void reintegrate(RTLIL::Module *module)
 						bit_drivers[i].insert(mapped_cell->name);
 			}
 		}
+		else if (delay_boxes.count(mapped_cell->name)) {
+			SigBit I = mapped_cell->getPort(ID(i));
+			SigBit O = mapped_cell->getPort(ID(o));
+			if (I.wire)
+				I.wire = module->wires_.at(remap_name(I.wire->name));
+			log_assert(O.wire);
+			O.wire = module->wires_.at(remap_name(O.wire->name));
+			module->connect(O, I);
+			continue;
+		}
 		else {
 			RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
 			log_assert(existing_cell);
@@ -620,6 +791,30 @@ void reintegrate(RTLIL::Module *module)
 					bit_drivers[i].insert(mapped_cell->name);
 			}
 
+			auto r2 = box_ports.insert(cell->type);
+			if (r2.second) {
+				// Make carry in the last PI, and carry out the last PO
+				//   since ABC requires it this way
+				IdString carry_in, carry_out;
+				for (const auto &port_name : box_module->ports) {
+					auto w = box_module->wire(port_name);
+					log_assert(w);
+					if (w->get_bool_attribute("\\abc9_carry")) {
+						if (w->port_input)
+							carry_in = port_name;
+						if (w->port_output)
+							carry_out = port_name;
+					}
+					else
+						r2.first->second.push_back(port_name);
+				}
+
+				if (carry_in != IdString()) {
+					r2.first->second.push_back(carry_in);
+					r2.first->second.push_back(carry_out);
+				}
+			}
+
 			int input_count = 0, output_count = 0;
 			for (const auto &port_name : box_ports.at(cell->type)) {
 				RTLIL::Wire *w = box_module->wire(port_name);
@@ -806,16 +1001,23 @@ struct Abc9OpsPass : public Pass {
 	{
 		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 
+		bool check_mode = false;
+		bool prep_times_mode = false;
 		bool break_scc_mode = false;
 		bool unbreak_scc_mode = false;
-		bool prep_dff_mode = false;
 		bool prep_holes_mode = false;
+		bool prep_dff_mode = false;
+		std::string write_box_src, write_box_dst;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
+			if (arg == "-check") {
+				check_mode = true;
+				continue;
+			}
 			if (arg == "-break_scc") {
 				break_scc_mode = true;
 				continue;
@@ -832,6 +1034,17 @@ struct Abc9OpsPass : public Pass {
 				prep_holes_mode = true;
 				continue;
 			}
+			if (arg == "-prep_times") {
+				prep_times_mode = true;
+				continue;
+			}
+			if (arg == "-write_box" && argidx+2 < args.size()) {
+				write_box_src = args[++argidx];
+				write_box_dst = args[++argidx];
+				rewrite_filename(write_box_src);
+				rewrite_filename(write_box_dst);
+				continue;
+			}
 			if (arg == "-reintegrate") {
 				reintegrate_mode = true;
 				continue;
@@ -844,12 +1057,17 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
-			log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
+		if (!(check_mode || break_scc_mode || unbreak_scc_mode || prep_times_mode || prep_holes_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
+			log_cmd_error("At least one of -check, -{,un}break_scc, -prep_{times,holes,dff}, -write_box, -reintegrate must be specified.\n");
 
 		if (dff_mode && !prep_holes_mode)
 			log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
 
+		if (check_mode)
+			check(design);
+		if (prep_times_mode)
+			prep_times(design);
+
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
 				continue;
@@ -866,10 +1084,12 @@ struct Abc9OpsPass : public Pass {
 				break_scc(mod);
 			if (unbreak_scc_mode)
 				unbreak_scc(mod);
-			if (prep_dff_mode)
-				prep_dff(mod);
 			if (prep_holes_mode)
 				prep_holes(mod, dff_mode);
+			if (prep_dff_mode)
+				prep_dff(mod);
+			if (!write_box_src.empty())
+				write_box(mod, write_box_src, write_box_dst);
 			if (reintegrate_mode)
 				reintegrate(mod);
 		}