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-rw-r--r--passes/techmap/dfflibmap.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index aa344cf8a..c189d649b 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
- char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
+ char from_clk_pol = from[8];
char from_set_pol = from[9];
char from_clr_pol = from[10];
- char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
- char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
+ char to_clk_pol = to[6];
+ char to_rst_pol = to[7];
char to_rst_val = to[8];
log_assert(from_clk_pol == to_clk_pol);
@@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
- char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
+ char from_clk_pol = from[6];
char from_rst_pol = from[7];
- char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
+ char to_clk_pol = to[6];
log_assert(from_clk_pol == to_clk_pol);
@@ -549,7 +549,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
struct DfflibmapPass : public Pass {
DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" dfflibmap [-prepare] -liberty <file> [selection]\n");
@@ -565,7 +565,7 @@ struct DfflibmapPass : public Pass {
log("liberty file.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");