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-rw-r--r--passes/techmap/insbuf.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index 2173049b4..0686c0f2b 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -41,16 +41,16 @@ struct InsbufPass : public Pass {
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
- std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y";
+ IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
std::string arg = args[argidx];
if (arg == "-buf" && argidx+3 < args.size()) {
- celltype = args[++argidx];
- in_portname = args[++argidx];
- out_portname = args[++argidx];
+ celltype = RTLIL::escape_id(args[++argidx]);
+ in_portname = RTLIL::escape_id(args[++argidx]);
+ out_portname = RTLIL::escape_id(args[++argidx]);
continue;
}
break;
@@ -76,9 +76,9 @@ struct InsbufPass : public Pass {
continue;
}
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
- cell->setPort(RTLIL::escape_id(in_portname), rhs);
- cell->setPort(RTLIL::escape_id(out_portname), lhs);
+ Cell *cell = module->addCell(NEW_ID, celltype);
+ cell->setPort(in_portname, rhs);
+ cell->setPort(out_portname, lhs);
log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
}