1 files changed, 15 insertions, 45 deletions

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 535db9465..c22ae8ef0 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -20,6 +20,7 @@
 #include "kernel/yosys.h"
 #include "kernel/utils.h"
 #include "kernel/sigtools.h"
+#include "kernel/ffinit.h"
 #include "libs/sha1/sha1.h"
 
 #include <stdlib.h>
@@ -328,8 +329,9 @@ struct TechmapWorker
 		for (auto tpl_cell : tpl->cells())
 		{
 			IdString c_name = tpl_cell->name;
+			bool techmap_replace_cell = (c_name == ID::_TECHMAP_REPLACE_);
 
-			if (c_name == ID::_TECHMAP_REPLACE_)
+			if (techmap_replace_cell)
 				c_name = orig_cell_name;
 			else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
 				c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
@@ -384,7 +386,7 @@ struct TechmapWorker
 			if (c->attributes.count(ID::src))
 				c->add_strpool_attribute(ID::src, extra_src_attrs);
 
-			if (c_name == ID::_TECHMAP_REPLACE_)
+			if (techmap_replace_cell)
 				for (auto attr : cell->attributes)
 					if (!c->attributes.count(attr.first))
 						c->attributes[attr.first] = attr.second;
@@ -425,18 +427,7 @@ struct TechmapWorker
 		LogMakeDebugHdl mkdebug;
 
 		SigMap sigmap(module);
-
-		dict<SigBit, State> init_bits;
-		pool<SigBit> remove_init_bits;
-
-		for (auto wire : module->wires()) {
-			if (wire->attributes.count(ID::init)) {
-				Const value = wire->attributes.at(ID::init);
-				for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
-					if (value[i] != State::Sx)
-						init_bits[sigmap(SigBit(wire, i))] = value[i];
-			}
-		}
+		FfInitVals initvals(&sigmap, module);
 
 		TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 		dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
@@ -642,6 +633,8 @@ struct TechmapWorker
 
 				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
 					parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
+				if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0)
+					parameters.emplace(ID::_TECHMAP_CELLNAME_, RTLIL::unescape_id(cell->name));
 
 				for (auto &conn : cell->connections()) {
 					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
@@ -658,15 +651,7 @@ struct TechmapWorker
 						parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
 					}
 					if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
-						auto sig = sigmap(conn.second);
-						RTLIL::Const value(State::Sx, sig.size());
-						for (int i = 0; i < sig.size(); i++) {
-							auto it = init_bits.find(sig[i]);
-							if (it != init_bits.end()) {
-								value[i] = it->second;
-							}
-						}
-						parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
+						parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), initvals(conn.second));
 					}
 				}
 
@@ -911,7 +896,7 @@ struct TechmapWorker
 								auto sig = sigmap(it->second);
 								for (int i = 0; i < sig.size(); i++)
 									if (val[i] == State::S1)
-										remove_init_bits.insert(sig[i]);
+										initvals.remove_init(sig[i]);
 							}
 						}
 					}
@@ -960,25 +945,6 @@ struct TechmapWorker
 			handled_cells.insert(cell);
 		}
 
-		if (!remove_init_bits.empty()) {
-			for (auto wire : module->wires())
-				if (wire->attributes.count(ID::init)) {
-					Const &value = wire->attributes.at(ID::init);
-					bool do_cleanup = true;
-					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
-						SigBit bit = sigmap(SigBit(wire, i));
-						if (remove_init_bits.count(bit))
-							value[i] = State::Sx;
-						else if (value[i] != State::Sx)
-							do_cleanup = false;
-					}
-					if (do_cleanup) {
-						log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
-						wire->attributes.erase(ID::init);
-					}
-				}
-		}
-
 		if (log_continue) {
 			log_header(design, "Continuing TECHMAP pass.\n");
 			log_continue = false;
@@ -991,7 +957,7 @@ struct TechmapWorker
 
 struct TechmapPass : public Pass {
 	TechmapPass() : Pass("techmap", "generic technology mapper") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1110,6 +1076,10 @@ struct TechmapPass : public Pass {
 		log("        When a parameter with this name exists, it will be set to the type name\n");
 		log("        of the cell that matches the module.\n");
 		log("\n");
+		log("    _TECHMAP_CELLNAME_\n");
+		log("        When a parameter with this name exists, it will be set to the name\n");
+		log("        of the cell that matches the module.\n");
+		log("\n");
 		log("    _TECHMAP_CONSTMSK_<port-name>_\n");
 		log("    _TECHMAP_CONSTVAL_<port-name>_\n");
 		log("        When this pair of parameters is available in a module for a port, then\n");
@@ -1151,7 +1121,7 @@ struct TechmapPass : public Pass {
 		log("essentially techmap but using the design itself as map library).\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
 		log_push();