diff options
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/dfflegalize.cc | 6 | ||||
| -rw-r--r-- | passes/techmap/extract.cc | 10 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
3 files changed, 12 insertions, 8 deletions
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 8ad65493f..c1e7e557d 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -418,7 +418,8 @@ unmap_enable: ff_type = has_set ? FF_ADFFE1 : FF_ADFFE0; break; } - if (supported_dffsr & initmask) { + if (supported_cells[has_en ? FF_DFFSRE : FF_DFFSR] & initmask) { +adff_to_dffsr: // Throw in a set/reset, retry in DFFSR/DFFSRE branch. if (has_set) { sig_s = sig_r; @@ -441,6 +442,9 @@ unmap_enable: ff_type = has_set ? FF_ADFF1 : FF_ADFF0; goto unmap_enable; } + if (supported_dffsr & initmask) { + goto adff_to_dffsr; + } log_assert(!((has_set ? supported_adff1 : supported_adff0) & initmask)); // Alright, so this particular combination of initval and // resetval is not natively supported. First, try flipping diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 7278cb680..f5966fac0 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -354,7 +354,7 @@ struct ExtractPass : public Pass { log("\n"); log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n"); + log("map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).\n"); log("\n"); log(" -map <map_file>\n"); log(" use the modules in this file as reference. This option can be used\n"); @@ -409,7 +409,7 @@ struct ExtractPass : public Pass { log("the following options are to be used instead of the -map option.\n"); log("\n"); log(" -mine <out_file>\n"); - log(" mine for frequent subcircuits and write them to the given ilang file\n"); + log(" mine for frequent subcircuits and write them to the given RTLIL file\n"); log("\n"); log(" -mine_cells_span <min> <max>\n"); log(" only mine for subcircuits with the specified number of cells\n"); @@ -578,7 +578,7 @@ struct ExtractPass : public Pass { } if (map_filenames.empty() && mine_outfile.empty()) - log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n"); + log_cmd_error("Missing option -map <verilog_or_rtlil_file> or -mine <output_rtlil_file>.\n"); RTLIL::Design *map = nullptr; @@ -606,7 +606,7 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); } - Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); f.close(); if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) { @@ -744,7 +744,7 @@ struct ExtractPass : public Pass { f.open(mine_outfile.c_str(), std::ofstream::trunc); if (f.fail()) log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); - Backend::backend_call(map, &f, mine_outfile, "ilang"); + Backend::backend_call(map, &f, mine_outfile, "rtlil"); f.close(); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 136c95d8e..d43737c8d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -983,7 +983,7 @@ struct TechmapPass : public Pass { log(" techmap [-map filename] [selection]\n"); log("\n"); log("This pass implements a very simple technology mapper that replaces cells in\n"); - log("the design with implementations given in form of a Verilog or ilang source\n"); + log("the design with implementations given in form of a Verilog or RTLIL source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); @@ -1210,7 +1210,7 @@ struct TechmapPass : public Pass { if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } |